2014 views|3 replies

661

Posts

0

Resources
The OP
 

Two circuits for modeling the behavior of a two-input AND gate [Copy link]

Behavioral modeling sequential logic circuit:
module and_gate1(clk, a, b, s);

input clk;
input a;
input b; output reg s; //Behavioral modeling sequential logic circuit (two-input AND gate) always @ (posedge clk) //Rising edge triggered begin s <= a & b; end endmodule Behavioral modeling combinational logic circuit: module and_gate2(a, b, s); input a; //Input signal a input b; //Input signal b output reg s; //Output signal c //Behavioral modeling combinational logic circuit (two-input AND gate) always @ (*) //Condition; * represents automatic search for the corresponding level value Level value trigger begin s = a & b; end endmodule























This post is from FPGA/CPLD
 

661

Posts

0

Resources
2
 

Two circuits for modeling the behavior of a two-input AND gate

This post is from FPGA/CPLD
 
 

661

Posts

0

Resources
3
 

Two circuits for modeling the behavior of a two-input AND gate

This post is from FPGA/CPLD
 
 
 

661

Posts

0

Resources
4
 

Two circuits for modeling the behavior of a two-input AND gate

This post is from FPGA/CPLD
 
 
 

Guess Your Favourite
Just looking around
Find a datasheet?

EEWorld Datasheet Technical Support

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号
快速回复 返回顶部 Return list