This project won the third prize in the 5th Electronic Design Competition of Zhejiang Sci-Tech University

Team number: ZSTU023

Team members: Feng Zelin, Luo Haolun, Wang Yuhang

Instructors: Lu Jun, Dai Yanyun

"School Level Electronic Design Competition" Design Summary Report

Topic: Low-frequency bi-phase sinusoidal signal generator (topic F) Awards: Third Prize in the Fifth Electronic Design Competition of Zhejiang Sci-Tech University

1 Design tasks and requirements

Design and produce a low-frequency bi-phase signal generator, which outputs two independent and independent sine waves, square waves, triangle waves, sawtooth waves, and modulated waves within a specific frequency range (programmable settings are available* **The amplitude, frequency and phase difference of the generated signal); and the waveform, frequency, amplitude and phase difference of the current two signal outputs are displayed on the LCD display and the waveform is displayed on the oscilloscope.

• basic requirements :
• (1) The two signals are independent and can be programmed to output sine waves, square waves, triangle waves and sawtooth waves; (10 points)
• (2) The maximum amplitude of the two signal outputs is not less than 3V, the amplitude of each channel is individually programmable and adjustable, and the setting resolution is 100mv; (10 points)
• (3) The frequency range of the two signals is adjustable from 1000Hz to 2000Hz, the step value is 10Hz, the frequency accuracy is not less than 1%, and the frequency and step value of each signal are individually programmable and adjustable; (10 points)
• (4) Generate two sinusoidal signals with the same frequency, and set the phase difference through program control, which can vary from 0 to 360 degrees in steps of 10 degrees; (10 points)
• (5) The duty cycle of the generated square wave and sawtooth wave is adjustable in the range of 1%-99%, and the setting resolution is not less than 1%; (10 points)
• Play part :
• (1) The maximum amplitude of the two signal outputs is not less than 6V, the amplitude of each channel is independently programmable and adjustable, and the setting resolution is not less than 10mv; (5 points)
• (2) The frequency step value of the two sinusoidal signals is not greater than 1Hz, and the frequency accuracy is not less than 0.1%; (5 points)
• (3) The phase difference setting resolution of two sinusoidal signals of the same frequency is not greater than 3 degrees; (10 points)
• (4) Generate analog amplitude modulation (AM) signal: the modulation degree ma can be program-controlled and adjusted between 10% and 100% in the range of 100KHz~1MHz, with a step of 10%, and the sinusoidal modulation signal frequency is 100Hz; - (10 minutes )
• (5) Generate analog frequency modulation (FM) signal: generate a maximum frequency deviation of 1KHz in the frequency range of 10KHz~1MHz. And the maximum frequency deviation can be divided into 500Hz/1KHz two-level program-controlled adjustment, and the sinusoidal modulation signal is 100Hz; (10 points)
• (6) Pattern output: can display patterns on the oscilloscope, for example: display W, V, L, N and other simple letter symbols. (10 points)
• illustrate:
• 1. ***Integrated DDS chips are not allowed to be used in the work, and DACs built into the microcontroller are not allowed to be used. ***If you use an integrated DDS chip, 5 points will be deducted; if you use a DAC built into the microcontroller, 5 points will be deducted.
• 2. The text of the design report should include the overall block diagram of the system, waveform generation principle, and main test results. Detailed circuit schematics, programs or circuit diagrams, and test results are provided in attachments.
• 3. The amplitude indicated in the indicator is ***peak-to-peak value***.

2 Low-frequency bi-phase sine signal generator module and software design

• 2.1 The FPGA core board is developed using the FPGA core board with Altera's Cyclone IV EP4CE6E22C8 as the core. The FPGA device is a semi-customized circuit in an application-specific integrated circuit. It is a programmable logic array and can effectively solve The original device has a small number of gate circuits. The basic structure of FPGA includes programmable input and output units, configurable logic blocks, digital clock management modules, embedded block RAM, wiring resources, embedded dedicated hard cores, and underlying embedded functional units. FPGA has been widely used in the field of digital circuit design because of its rich wiring resources, re-programmability, high integration, and low investment. Using the FPGA core board to produce this question, the requirements can be achieved through programming gate arrays to achieve the goal of complete program control.
• 2.2 STM32F103VCT6 core board Use the development board with STMicroelectronics' STM32F103VCT6 chip as the core to produce this question. The mainstream Cortex core has extremely high performance, rich and reasonable peripherals, powerful software support and comprehensive and rich technical documentation, making the STM32 development board the best choice for electronic design competitions.
• 2.3 DAC module uses DAC900, a high-performance digital-to-analog converter with 10-bit resolution and 165MBPS high-speed differential current output. The ultra-high speed fully meets the requirements of this question. Under a 5V power supply condition, it is impossible to achieve a peak-to-peak value of 6V. Therefore, the differential output of the DAC900 is used to convert the differential current output into a single-ended positive and negative voltage output. The maximum value only needs to reach ±3V, which can easily achieve the amplitude requirement. .
• 2.4 Post-amplification circuit Use OPA695 to build a non-inverting amplifier. OPA695 is an ultra-wideband current feedback amplifier with extremely high conversion rate and ultra-wide bandwidth, and has high applicability.
• 2.5 System software design
• 2.5.1 After the FPGA system is reset, it outputs a full-scale 1KHz sine wave by default, detects and receives STM32 commands through the I/O port, and processes the output waveform according to the commands. STM32 pulls down all I/O port levels by default. When the keyboard issues a command, it pulls up the corresponding I/O port level, and the FPGA judges it and executes the command.
• 2.5.2 After the STM32 system is started, perform system initialization and LCD initialization, wait for key interruption, and confirm that a key is pressed if a key is pressed, and perform corresponding processing according to the value returned by the key. The parameters include channel selection, waveform, frequency, phase, duty cycle, and amplitude.
• flow chart:

• Works picture:

STM32 and FPGA codes have been open sourced.