The circuit shown in Figure 1 monitors the current in the system and operates at positive high common-mode DC voltages up to +500 V with an error of less than 0.2%. The load current passes through a shunt resistor external to the circuit. The shunt resistor value should be chosen so that the shunt voltage is approximately 500 mV at maximum load current.

When used with external PNP transistors, the AD8212 can accurately amplify small differential input voltages with high positive common-mode voltages greater than 500 V.

Galvanic isolation is provided by the ADuM5402 quad-channel isolator . This is not only for protection, but also to isolate downstream circuitry from high common-mode voltages. In addition to isolating the output data, the ADuM5402 digital isolator provides +3.3 V isolated power to the circuit.

AD7171 measurement results are provided as digital codes through a simple two-wire SPI-compatible serial interface.

This combination of devices enables an accurate positive high-voltage supply rail current sensing solution with low component count, low cost, and low power consumption.

This circuit is designed for a full-scale shunt voltage of 500 mV at maximum load current IMAX. Therefore, the shunt resistor value is RSHUNT = (500 mV)/(IMAX).

The AD8212 process has a breakdown voltage limit of 65 V. Therefore, the common-mode voltage must be kept below 65 V. By using an external PNP BJT transistor, the common-mode voltage range can be extended to over 500 V, depending on the breakdown voltage of the transistor.

The AD8212 does not have a dedicated power supply. Instead, the device actually uses an internal 5 V series regulator to "float" itself off the 500 V common-mode voltage, creating a 5 V supply, as shown in Figure 2. This regulator ensures that the largest negative terminal of all terminals, COM (pin 2), is always 5 V below the supply voltage (V+).

In this mode of operation, the supply current (I _BIAS ) of the AD8212 circuit is entirely based on the supply voltage range and the selected R _BIAS resistor value. For example, for V+ = 500 V and RBIAS ₌ 500 kΩ,

IBIAS = (500 V −5 V)/RBIAS _{= 990} μA.

In this high-voltage mode, I _BIAS should be between 200 μA and 1 mA. This ensures that the bias circuit is active, allowing the device to operate properly.

Note that the 500 kΩ bias resistor (5 × R2) consists of five separate 100 kΩ resistors. This is to provide protection against resistor voltage breakdown. Additional breakdown protection can be added by eliminating the ground plane directly beneath the resistor string.

The load current flowing through the external shunt resistor produces a voltage at the input of the AD8212. Internal amplifier A1 responds by causing transistor Q1 to conduct the necessary current through resistor R1 to equalize the potentials at the inverting and non-inverting inputs of amplifier A1.

The current flowing through the emitter of transistor Q1 (I _OUT ) is proportional to the input voltage (V _SENSE ) and therefore to the load current (R _{SHUNT ) flowing through the shunt resistor (I LOAD} ) . The output current (I _OUT ) is converted to a voltage through an external resistor whose value depends on the input-to-output gain required in the application.

The transfer function of AD8212 is:

I _OUT = gm × V _SENSE
V _SENSE = I _LOAD × R _SHUNT
V _OUT = I _OUT × R _OUT
V _OUT = (V _SENSE × R _OUT )/1000 gm = 1000 μA/V

The input sense voltage has a fixed range of 0 V to 500 mV. The output voltage range can be adjusted based on the R _OUT value. A 1 mV change in VSENSE produces a 1 mA change in I _{OUT , which in turn produces a 1 mV change in V OUT} when it flows through a 5 kΩ resistor .

In the circuit shown in Figure 1, the load resistance is 24.9 kΩ, so the gain is 5. A full-scale input voltage of 500 mV produces a 2.5 V output, which corresponds to the full-scale input range of the AD7171 ADC.

The AD8212 output is designed to drive high impedance nodes. Therefore, if interfacing with a converter, it is recommended to buffer the output voltage across R _{OUT to ensure that the gain of the AD8212 is not affected.}

Note that the supply voltage for the ADR381 and AD7171 is provided by the isolated power output (+3.3 V _ISO ) of the ADuM5402 quad isolator .

The reference voltage of the AD7171 is provided by the precision bandgap reference voltage source ADR381. The ADR381 has an initial accuracy of ±0.24% and a typical temperature coefficient of 5 ppm/°C.

Although both the AD7171 VDD and REFIN(+) can operate from 3.3 V supplies, using separate voltage references provides greater accuracy. A 2.5 V reference can be selected to provide ample headroom.

The input voltage to the AD7171 ADC is converted to an offset binary code at the output of the ADC. The ADuM5402 provides isolation for the DOUT data output, SCLK input, and PDRST input. Although the isolator is optional, it is recommended to protect downstream digital circuitry from high common-mode voltages during fault conditions.

The code is processed in PC using SDP hardware board and LabVIEW software.

The graph in Figure 4 shows how the circuit under test achieved less than 0.2% error over the entire input voltage range (0 mV to 500 mV). In addition, the ADC output code recorded by LabVIEW was compared with the ideal code calculated based on the ideal system.

PCB layout considerations

In any circuit where precision is important, power and ground return layout on the circuit board must be carefully considered. The PCB should isolate the digital and analog parts as much as possible. This PCB is made of 4-layer boards stacked with large area polygons for the ground layer and power layer. For information on decoupling techniques, see Tutorial MT-101 .

The supplies for the AD7171 and ADuM5402 should be decoupled with 10 μF and 0.1 μF capacitors for proper noise rejection and ripple reduction. These capacitors should be as close to the corresponding devices as possible, and the 0.1 F capacitors should have low ESR values. For all high frequency decoupling, ceramic capacitors are recommended.

The isolation gap between the primary and secondary sides of the ADuM5402 should be carefully considered. The EVAL-CN0218-SDPZ board maximizes this distance by pulling back the polygons or devices on the top layer and aligning them with the pins on the ADuM5402.

Power traces should be as wide as possible to provide a low impedance path and reduce the effects of glitches on the power lines. Clocks and other fast-switching digital signals should be digitally shielded from other devices on the board.

For a complete design support package for this circuit note, including board layout, see http://www.analog.com/CN0218-DesignSupport .