The circuit shown in Figure 1 is a flexible signal conditioning block that offers low noise, relatively high gain, and the ability to dynamically change gain as input levels change without affecting performance, while still maintaining a wide dynamic range. Existing sigma-delta technology can provide the dynamic range required by many applications, but at the expense of low update rates. This circuit provides an alternative method of using the AD7985 16-bit, 2.5 MSPS PulSAR® ^successive approximation _ADC with an autoranging  iCMOS® programmable gain instrumentation amplifier (PGA) AD8253 front end. Because the gain automatically changes based on the analog input value, the device uses oversampling and digital processing to increase the system dynamic range to more than 125 dB.

Many applications require wide dynamic range. Scale systems typically use load cell bridge sensors with a maximum full-scale output of 1 mV to 2 mV. Such systems may require resolutions at the 1,000,000:1 level, using a 2 mV full-scale input as an example, requiring high-performance, low-noise, high-gain amplifiers and sigma-delta modulators. Likewise, chemistry and blood analysis in medical applications often use photodiode sensors, which generate extremely small currents and require precise measurement. Some applications, such as vibration monitoring systems, contain both AC and DC information, so the ability to accurately monitor both large and small signals is critical. Σ-Δ ADCs, while competent in many situations, are limited if AC and DC measurements and fast gain switching are required.

Oversampling is the process of sampling an input signal at a rate much higher than the Nyquist frequency. Generally speaking, every time the sampling frequency is doubled, the noise performance within the original signal bandwidth can be improved by approximately 3 dB. The oversampling ADC is followed by digital post-processing to remove noise outside the signal bandwidth, as shown in Figure 2.

To achieve maximum dynamic range, a front-end PGA stage can be added to increase the effective signal-to-noise ratio (SNR) at very small signal inputs. Consider a system dynamic range requirement of >126 dB. First calculate the minimum rms noise required to achieve this dynamic range. For example, a 3 V input range (6 V pp) has a full-scale rms value of 2.12 V (6/2√2). The maximum allowable system noise is calculated as follows

126 dB = 20 log (2.12 V/rms noise)

Therefore the rms noise ≈ 1 µV rms.

Now consider the system update rate, which determines the oversampling rate and maximum amount of noise allowed by the system (referenced to the input (RTI)). For example, when the 16-bit, 2.5 MSPS PulSAR ADC AD7985 operates at 600 kSPS (consuming 11 mW) and an oversampling rate of 72x, the effective system throughput rate after averaging and decimation is 600 kSPS ÷ 72 = 8.33 kSPS. The input signal is therefore limited to a bandwidth of approximately 4 kHz.

The total rms noise is the noise density (ND) times √f. The maximum allowable input spectral noise density (ND) can be calculated as follows

1 µV rms = ND × √4 kHz

That is ND = 15.8 nV/√Hz.

Based on this figure of merit for the RTI system input noise, an appropriate instrumentation amplifier can be selected to provide sufficient analog front-end gain (added to the ADC SNR via correlated oversampling) to achieve the required 126 dB. For the AD7985 , the typical SNR value is 89 dB, and an improvement of ~18 dB is obtained by oversampling by a factor of 72 (72 is approximately 2 ⁶ , with an increase of 3 dB for each doubling). Achieving 126 dB DR still requires another 20 dB of improvement, which can come from the gain provided by the analog PGA stage. The instrumentation amplifier must provide a gain of ≥20 (as long as the noise density specification of 15.8 nV/√Hz is not exceeded).

Figure 1 shows the system-level solution to achieve the front-end PGA gain and ADC oversampling described above. The input stage uses the AD8253 - an extremely low noise (10 nV/√Hz) digitally controlled instrumentation amplifier. Gain options are as follows: G = 1, 10, 100, 1000.

The AD8021 is a 2.1 nV/√Hz low noise, high speed amplifier capable of driving the AD7985 . This device also level shifts and attenuates the AD8253 output. The AD8253 and AD8021 both operate with an external common-mode bias voltage of 2.25 V, which combine to maintain the same common-mode voltage at the input of the ADC. With a reference voltage of 4.5 V, the input range of the ADC is 0 V to 4.5 V.

The output of the AD8021 is measured using a high speed ADC. The PGA gain can be dynamically set based on the amplitude of the input signal. For small signal input, the gain is set to 100. For larger inputs, the gain is reduced to 1.

Digital post-processing is implemented using the AD7985 , a 16-bit, 2.5 MSPS PulSAR ADC in a QFN package (consuming 11 mW). Due to its fast sampling rate, the device can also be used to implement high-order oversampling in low input bandwidth applications. Given that the complete system noise budget is 15.8 nV/√Hz (max) referenced to the input (RTI), the dominant noise sources for each module can be calculated to ensure that the hard limit of 15.8 nV/√Hz is not exceeded. The input-referred noise specification of the AD8021 is <3 nV/√Hz, which is negligible when referred to the AD8253 stage with a gain of 100. The AD7985 has a specified SNR of 89 dB with a noise resolution of <45 µV rms using an external 4.5 V reference .

If we consider the Nyquist bandwidth of 300 kHz, the ADC will provide ~83 nV/µHz noise within this bandwidth. When referred to the input of the AD7985 , its <1 nV/√Hz noise is negligible in the system. At this time, a root-sum-square calculation is used to sum the RTI noise sources.

Another advantage of using the AD8253 is that it has a digital gain control function that can dynamically change the system gain based on input changes. This is achieved through clever use of the system's digital signal processing capabilities. In this application, the primary function of digital processing is to produce a higher resolution output using the AD7985 16-bit conversion results. The implementation method is to average and decimate the data and automatically switch the analog input gain according to the input amplitude. The output data rate of the oversampling process is lower than the ADC sampling rate, but the dynamic range is greatly increased.

To complete the prototyping of the digital side of this application, a field programmable gate array (FPGA) is used as the digital core. In order to quickly debug the system, the analog circuit and FPGA are integrated on a single circuit board using the System Demonstration Platform (SDP) connector standard to easily implement USB connection to the PC, as shown in Figure 3. SDP is a combination of reusable hardware and software that can easily implement hardware control and data acquisition on most common component interfaces.

This module outputs a new gain setting based on the current gain setting, two raw ADC samples, and some hard-coded thresholds. Four thresholds are used within the system. The selection of these thresholds is important to maximize the analog input range of the system, ensuring that G=100 mode is used over the widest possible signal range while preventing overdriving of the ADC inputs. Note that this gain block processes each raw ADC result, not the unnormalized data. Given this premise, some examples of thresholds that can be used in the system are as follows (assuming a bipolar system with zero midlevel):

T1 (lower positive threshold): +162

(162 codes above mid-level)

T2 (lower negative threshold): –162

(162 codes below mid-level)

T3 (upper positive threshold): +32507

(260 codes below positive full scale)

T4 (upper negative threshold): -32508

(260 codes above negative full scale)

In G=1 mode, internal limits T1 and T2 are used. If the actual ADC result is between T1 and T2, the gain switches to G = 100 mode. This ensures that the ADC's analog input voltage is maximized as quickly as possible. Next, in G = 100 mode, the external limits T3 and T4 are used. If the predicted ADC result is above T3 or below T4, the gain is switched to G = 1 mode to prevent the ADC input from going over range, as shown in Figure 4.

In G = 100 mode, if the algorithm predicts that the next ADC sample will be just above the external threshold (using the most basic linear prediction), assuming the ADC result is +32510, then the gain switches to G = 1 and the next ADC result is +325 Instead of +32510.

Overall system performance

Once the gain and decimation algorithms are fully optimized, the entire system can be tested. Figure 5 shows the system response to a large signal 1 kHz input tone of –0.5 dBFS. When considering a PGA gain of 100, the achieved dynamic range is 127 dB. Similarly, when testing the small signal input in Figure 6, if the input tone is 70 Hz (at –46.5 dBFS), a maximum dynamic range of 129 dB can be achieved. Since no effective switching of the gain range occurs in this measurement, performance improvements are expected at smaller input tones.

System performance depends on the ability to dynamically switch gains to handle both small and large signal inputs. While Σ-Δ technology provides excellent dynamic range, SAR-based solutions are also a way to dynamically change the front-end gain based on the input signal without affecting system performance. This allows real-time measurement of small and large signal AC and DC inputs without having to wait for system settling time or causing large glitches due to delayed gain changes.