These factors must be considered in signal chain design:

• AD2S1210 excitation signal output range: 3.2 V (minimum value), 3.6 V (typ. value), 4.0 V (maximum value)
• AD8692 output voltage range: 0.29 V to 4.6 V when powered by +5 V supply
• AD8397 output voltage range: 0.18 V to 5.87 V when powered by +6 V supply
• AD8397 output voltage range: 0.35 V to 11.7 V when powered by +12 V supply
• Resolver (TS2620N21E11) transformation ratio: 0.5
• Resolver (TS2620N21E11) phase shift: 0°
• AD8694 output voltage range: 0.37 V to 4.6 V when powered by +5 V supply
• AD2S1210 input differential peak-to-peak signal range (SIN, COS): 2.3 V (minimum), 3.15 V (typ), 4.0 V (max)
• The resolver output SIN and COS loads should be equal
• The resolver output load should be at least equal to 20 times the resolver output impedance.
• Total signal chain phase shift range: n × 180° − 44° ≤ φ ≤ n × 180° + 44°, n is an integer

The AD2S1210 excitation signal filter and power amplifier circuit is shown in Figure 2. Close attention must be paid to the gain and signal levels of each part of the signal chain to avoid saturating the AD8397 output driver at the 4.0 V pp maximum excitation (EXE) of the AD2S1210. Note that since the resolver is driven differentially, there are two identical channels corresponding to the true EXE output and the complementary EXE output, as shown in Figure 2.

The DC gain of the AD8692 filter circuit is −1. For high performance mode (S1 off), the gain of the AD8397 driver stage is set to 2.5 (or 2.49 if using the actual available resistors), so that a 4.0 V pp EXE input produces a 10 V pp output when powered from a 12 V supply. This will allow the output of the AD8397 to have 1 V headroom relative to each supply rail. For low-power mode (S1 on), the gain is set to 1.28 so that a 4.0 V pp EXE input produces a 5.12 V pp output when powered from a 6 V supply.

The ADG1612 has a typical on-resistance of less than 1 Ω, making it suitable for gain switching. However, since the switch's turn-off capacitance is typically 72 pF, it should not be connected directly to the input of the op amp. Note that in the circuit, R6 is connected to ground, which has minimal impact on performance when the capacitor is turned off.

The AD8692 is configured as a multiple feedback (MFB) third-order Butterworth low-pass filter with a phase shift range of 180° ± 15°. See the linear circuit design manual (Chapter 8) for design steps . It is important to select the appropriate op amp for this filter. Generally speaking, the gain-bandwidth product of the op amp should be at least 20 times greater than the –3dB cutoff frequency of the active filter. In this case, the cutoff frequency is 88 kHz, and the gain-bandwidth product of the AD8692 is 10 MHz, or 113 times the cutoff frequency. Since the AD8692 is a CMOS operational amplifier, its input bias current is extremely low and will not have a great impact on the DC characteristics of the filter. The input capacitance is 7.5 pF, which minimizes the impact of the cutoff frequency on the capacitance selected in the filter design.

The filter has a −3dB cutoff frequency of 88 kHz, a phase shift of −13° at 10 kHz, and a DC gain of 1 at 10 kHz.

The AD8397 power amplifier gain is configurable to 1.28 (low gain mode) or 2.49 (high gain mode). In low-gain mode, the phase shift at 10 kHz is equal to −1.9°, and in high-gain mode, the phase shift is equal to −5.2°.

The AD8692 third-order low-pass filter transfer function is shown in Figure 3.

This filter is extremely effective at reducing noise generated by the excitation signal driving the resolver. Figure 4 shows a 10 kHz EXE signal measured directly at the output of the AD2S1210. Figure 5 shows the measured signal at C3 (input to the AD8397) and how effectively the filter filters the noise. 

 

 

 

Figure 4. Signal measured at AD2S1210EXC pin

 

 

 

Figure 5. Signal measured on C3 (input to AD8397 driver)

Figures 6 and 7 show the AD8397 output measured at one input of the resolver in low-power mode and high-performance mode, respectively. Note that these signals are measured on one side of the resolver input, whereas the actual differential signal applied to the resolver has double the amplitude.

 

 

 

Figure 6. Signal at resolver input when using low power mode

 

 

 

Figure 7. Signal at resolver input when using high performance mode

Figure 8 shows the receiver circuit, including a third-order Butterworth filter and programmable gain stage. When the driver circuit is in high performance mode (VCC = 12 V), S1 is on and the total gain is 0.35. The input driving the resolver is 18 V pp (differential), and since the resolver has a conversion ratio of 0.5, the SIN/COS output is 9 V pp differential. 9 V pp differential equals 4.5 V pp single-ended, which when multiplied by a 0.35 gain factor gives 1.58 V pp (3.16 V pp differential), the optimal input voltage for the AD2S1210SIN/COS input. Similarly, in low-power mode, S1 is off and the total gain is 0.7, again providing optimal input signal levels for the SIN/COS input of the AD2S1210. 

Figure 8. Resolver receiver circuit (schematic diagram: all connections and decoupling not shown)

In addition to providing gain adjustment, the receiver circuit also features a third-order Butterworth filter with a cutoff frequency of 63 kHz and a phase shift of −18.6° at 10 kHz.

The frequency response of the filter in low gain mode and high gain mode is shown in Figure 9 and Figure 10 respectively.

 

 

 

Figure 10. Resolver receiver circuit, high gain transfer function 

 

The voltage at the AD2S1210SIN/COS input terminal is shown in Figure 11 (1.64 V pp, 3.28 V pp differential)

Figure 12 shows that the total phase shift from the AD2S1210EXC pin (channel 1, yellow) to the SIN input pin (channel 2, blue) is approximately 40°, which is below the maximum design value of 44°. 

 

 

 

Figure 12. Phase shift between AD2S1210EXC and SIN pins

Automatic mode detection circuit

 

The reset circuit shown in Figure 13 uses the ADM6328 microprocessor reset circuit, which can determine the gain of the driver and receiver based on the VCC voltage value. The threshold voltage is set so that if VCC is higher than 11.5 V, then the circuit will switch to high performance mode. If VCC falls below 11.5 V, then the circuit switches to low power mode.

Because the ADM6328 consumes only 1 A, the device can use the high-impedance R1/R3 resistor divider output as its power supply without incurring a large voltage drop.

The ADM6328 has an open-drain output and resistor R2 acts as a pull-up resistor. This ensures that the output swing is independent of the VCC input. The ADM6328 supply voltage is determined by the following equation

 

 

The circuit uses the ADM6328-22, which has a typical threshold voltage of 2.2 V and a maximum of 2.25 V. The maximum VCC threshold voltage is 11.5 V, therefore:

 

 

R1 and R3 are selected as 1.6 Ω k and 390 Ω respectively, and the ratio is 4.102.

 

Resolver driver power amplifier power consumption

Because of the relatively low impedance and large VCC voltage of the resolver, it is important to understand the power dissipation of the AD8397 driver amplifier to ensure that the maximum power dissipation specifications are met. The maximum power dissipation of the AD8397 for safe operation is limited by the increase in junction temperature.

The maximum safe junction temperature of plastic-encapsulated devices is determined by the phase transition temperature of the plastic, which is approximately 150°C. Even if this limit is exceeded only temporarily, parametric performance may change due to changes in the stresses exerted by the package on the chip.

The rise in junction temperature can be calculated based on the ambient temperature (TA ₎ , package thermal resistance (θ _JA ), and amplifier power dissipation (P _AMP ):

 

 

This circuit uses the AD8397ARDZ, which is available in an 8-pin SOIC package with exposed pad (EP) and θ _JA = 47.2°C/W.

The amplifier power consumption P _AMP is calculated as follows: Subtract the load power consumption P _{LOAD from the power consumption P SUPPLY} provided by the power supply. The equivalent load impedance of the resolver rotor winding is equal to:

 

The power consumption provided by the power supply can be calculated by first calculating the average current drawn from the power supply. Note that these calculations ignore the op amp's quiescent current and only consider the current generated by the excitation current. The equivalent circuit for these calculations is shown in Figure 14.

Figure 14. Equivalent circuit for calculating supply current 

 

When using the Tamagawa TS2620N21E11 resolver, the impedance at 10 kHz is 70 +j100. In the high performance state (VCC = 12 V, A = 10 V), using the derived equation above, the AD8397 power dissipation is calculated to be 390 mW. The junction-to-ambient thermal resistance θJA of the AD8397 (EP package) is 47.2°C/W, so the junction temperature rising above ambient temperature is 47.2°C/W × 0.39W = 18.4°.

power supply

The entire circuit is powered from an external VCC of +6 V or +12 V, depending on the operating mode. The circuit's 5 V supply comes from a 5 V, 500 mA low dropout regulator (LDO) ADP7104-5 . The 3.3 V ADP7104-3.3 is used to provide the 3.3 V power supply. For detailed power circuitry see the complete schematic in the CN0276 Design Support Package

PCB design and layout considerations

Poor layout can result in poor performance, even at the lower frequencies associated with the RDC circuit. For example, although the resolver operates with a 10 kHz excitation signal, the AD2S1210 operates with an 8.192 MHz clock; therefore, it must be treated as a high-speed device when laying out, grounding, and decoupling it. Tutorial MT-031 and Tutorial MT-101 discuss these topics in detail

A design support package is provided for the CN-0276, including complete schematics, PA D and Gerber layout files, and a bill of materials. The design support package is located at: http://www.analog.com/CN0276-DesignSupport .

System performance results

A good way to measure the overall system noise of a circuit is to fix the resolver position and generate a histogram of the output codes. This test should be performed with hysteresis disabled. The figure below shows the code histogram output by the AD2S1210 (10/12/14/16-bit angle accuracy mode). The full 16-bit RDC is used to generate the histograms in each case, with the circuit in high-performance mode (VCC = +12 V).

Histograms show that the AD2S1210 with integrated low-pass filters on the driver and receiver circuits achieves high angular resolution in all modes

 

 

 

Figure 16. Output code histogram, 10,000 samples, hysteresis disabled, 12-bit angle accuracy mode, 16-bit ADC resolution

 

 

 

Figure 17. Output code histogram, 10,000 samples, hysteresis disabled, 14-bit angle accuracy mode, 16-bit ADC resolution

 

 

 

Figure 18. Output code histogram, 10,000 samples, hysteresis disabled, 16-bit angle accuracy mode, 16-bit ADC resolution