Anlu SparkRoad Development Board Review (6) Use of FIFO IP

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Anlu SparkRoad Development Board Review (6) Use of FIFO IP [Copy link]

 

　　FIFO IP in FPGA plays an important role as a buffer in data transmission. In particular, asynchronous FIFO can easily solve the problem of cross-clock synchronization.

　　TD provides FIFO IP resources, but compared with the FIFO IP of the Altera Cyclone series that I am most familiar with, the configuration is much simpler. In the IP Generator dialog box, there are two types of IP: FIFO and RAMFIFO.

　　Let’s first look at the FIFO IP selection.

　　It can be configured as synchronous or asynchronous FIFO. The input data bit width can be selected in a wide range, and the input and output can have different widths. There are five levels of FIFO depth, with a minimum of 512 and a maximum of 8192. In addition to the empty and full flag outputs, you can also select the almost full and almost empty flags, but there is no current FIFO data output.

　　Synthesize a FIFO with a width of 8 bits and a depth of 512, and the resulting resource usage is:

　　Under the bram group, a fifo9k resource is used, which is different from bram9k. In addition, the usage of LE is very small. It seems that the implementation of FIFO uses a special resource, which is not available in the altera FPGA I have used. The latter is implemented with RAM plus logic. Therefore, the implementation of FIFO in Anlu FPGA may be more efficient.

　　What is another RAMFIFO IP like?

　　It is also an asynchronous FIFO, but the configuration interface is different and simpler. The input and output data bits must be equal. The implementation method is to use block RAM. The output of the FIFO data volume is provided here. It can be inferred that the implementation method is different from the previous IP.

　　Let's take a look at the resource usage of a RAMFIFO that is also 8x512:

　　This time, a lot of LE resources are used. It is indeed built with RAM and logic. Because of the increased data output, more logic will be used.

　　Let's do a simple demonstration. In order to use the SparkRoad board itself to demonstrate the effect of FIFO, use switches to specify FIFO input and digital tubes to display FIFO output data.

　　The clocks for reading and writing FIFOs are strictly asynchronous, so I also used a PLL and reduced the frequency of both the read and write clocks for easier observation.

　　The design is that every time the button is pressed, a batch of data is written to the FIFO: the switch is used to set the number of writes (1~255) and the value of the first data (0~255), and the subsequent data values increase in sequence.

　　When there is data in FIFO, the data is read and displayed on the digital tube in decimal form.

　　The asynchronous FIFOs implemented by the two IPs have the same operation effects, but the resource usage of the entire project will be different:

Jacktang

The asynchronous FIFOs implemented by the two IPs are both easy to use and have their own advantages.