CLOCK_DEDICATED_ROUTE constraint applies

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CLOCK_DEDICATED_ROUTE constraint applies [Copy link]

The Vivado tool usually automatically identifies the clock network in the design during compilation and assigns it to the dedicated clock placement and routing resources. By setting the CLOCK_DEDICATED_ROUTE value to FALSE for certain clock networks , the clock signals that are identified as clock networks and placed and routed according to the clock networks can be arranged into the general routing resources. For example, some clock signals are not arranged on the dedicated clock pins of the FPGA device due to design negligence or other reasons, and an error will be reported during compilation. At this time, the CLOCK_DEDICATED_ROUTE constraint can be used to ignore this error.

Example 1 : Ignore compilation errors about clock routing

We have a design that inputs the image data synchronization clock image_sensor_pclk signal to the FPGA . Since it is not assigned to the MRCC or SRCC pin inside the FPGA , Vivado may usually report an error during compilation .

At this point, we can ignore this error and allow compilation to continue by adding the following CLOCK_DEDICATED_ROUTE command to the .xdc constraint file of the project .

Of course, it is usually not recommended to abuse this constraint. The clock network with CLOCK_DEDICATED_ROUTE FALSE applied will be allocated to the general layout and routing resources. If this is a clock on a timing-critical path, such behavior is likely to cause some unexpected design problems.

Example 2 : View clock resources

For a compiled project, click Run Implementation to open the implementation interface.

At this point, many visual report items appear in the Reports menu. Click Report Clock Utilization .

At this point, in the Clock Utilization interface, you can view all the networks that occupy clock placement and routing resources in the current project.