FPGA timing constraints video tutorial

With the advancement of technology, the application scenarios of FPGA are becoming wider and wider, from the previous fields of control and communication to the fields of parallel accelerated computing, artificial intelligence algorithm acceleration, etc. However, no matter the ever-changing applications, timing constraints are the most important in FPGA. One of the links, it is also the blind spot of many FPGA engineers. This tutorial explains in detail the various timing constraint theories of FPGA, and takes an actual Vivado project as an example to carry out timing constraints step by step, and finally achieve timing closure.

• Chapter 1：setup time hold time (4 minutes and 31 seconds)

• Chapter 2：Timing Path Timing Model (5 minutes and 54 seconds)

• Chapter 3：IO constraints (4 minutes and 44 seconds)

• Chapter 4：clock cycle constraints (20 minutes and 6 seconds)

• Chapter 5：Two timing exceptions (20 minutes and 22 seconds)

• Chapter 6：xdc constraint priority (4 minutes and 15 seconds)

• Chapter 7：Combing the clock tree (4 minutes and 44 seconds)

• Chapter 8：Practical Chapter Master Clock Constraints (3 minutes and 40 seconds)

• Chapter 9：Derived Clock Constraints in Practical Combat (4 minutes and 14 seconds)

• Chapter 10：Delay Constraints in Practical Combat (3 minutes and 52 seconds)

• Chapter 11：Pseudo path constraints in practical combat (3 minutes and 17 seconds)

• Chapter 12：Practical Chapter: Multi-Cycle Path Constraints (6 minutes and 49 seconds)

• Chapter 13：Vivado Timing Constraint Assistant Tool (2 minutes and 15 seconds)

• Chapter 14：Objects and attributes of Tcl commands (6 minutes and 11 seconds)