Location:Training / Embedded Development / FPGA / Verilog HDL design and practice / Application of Interval Timer core

"Verilog HDL Design and Practice" is divided into four parts: basic operations of the ModelSim simulation tool and QuartusⅡ development tool, Verilog HDL syntax introduction, FPGA example design and NiosⅡ example design based on Qsys. First, the basic operations of QuartusII are introduced, including project creation, code editing, schematic design, VerilogHDL code design, waveform simulation based on QuartusII and ModelSim, and downloading of FPGA configuration files and other basic operations related to FPGA design. Then, the basic syntax of VerilogHDL is introduced one by one in the form of VerilogHDL knowledge points with VerilogHDL program examples. Then, using examples as the starting point, from simple to complex, the modeling of combinational circuits, sequential circuit modeling and the design of comprehensive examples are introduced.