Two Design Methods for Low Noise Amplifiers

The low noise amplifier (LNA) is an important part of the RF transceiver. It can effectively improve the receiver's receiving sensitivity and thus increase the transmission distance of the transceiver. Therefore, whether the design of the low noise amplifier is good or not is related to the communication quality of the entire communication system. This article takes the transistor ATF54143 as an example to illustrate the design methods of two different low noise amplifiers. Its frequency range is 2~2.2 GHz; the transistor operating voltage is 3 V; the operating current is 40 mA; the input and output impedance is 50Ω.
1 Qualitative Analysis

1.1 Transistor Modeling

You can check the relevant information of transistor manufacturers through the Internet, download the transistor model provided by the manufacturer, or download the S2P file of the tube according to actual needs. In this example, the S2P file of the tube is directly imported into the software, and the circuit is designed using the S parameters as the model. If it is the first time to import, you can use the module SParams to perform S parameter simulation, observe whether the obtained S parameters are the same as the data provided by the S2P file, and at the same time, measure the input impedance of the transistor and the corresponding minimum noise factor, and judge the stability of the transistor, etc., to prepare for the next step.

1.2 Transistor stability

After completing the S parameter simulation of the circuit, it can be obtained that the mu of the input/output end is less than 1 between the frequencies of 2 and 2.2 GHz. According to the RF related theory, the transistor is unstable. By connecting a 10 Ω and 5 pF capacitor in parallel at the output end, the values ​​of m2 and m3 are both greater than 1, as shown in Figure 1 and Figure 2. The transistor achieves conditional stability within the bandwidth, and the input impedance at 2.1 GHz is measured to be 16.827-j16.041. At the same time, it is found that due to the addition of a resistor at the output end, Fmin increases from 0.48 to 0.573, Topt is 0.329 ∠125.99°, and Zopt = (30.007 +j17.754) Ω. Among them, Topt is the optimal source reflection coefficient.

Figure 1. Circuit schematic diagram for simulation using SParams module

Figure 2 Relationship between input/output mu and frequency

1.3 Develop a plan

As shown in Figure 3, the available gain circle family and the noise coefficient circle family are drawn on the same Ts plane. Through analysis, it can be seen that if the available gain circle passes through the position of the optimal noise coefficient point and the input circuit matching is performed based on this point, then for LNA, the noise coefficient is the minimum, but its gain does not reach the optimal amplification. Therefore, it is obtained by sacrificing the available gain. In this case, the transistor gain can reach about 14 dB, and Fmin is about 0.48, as shown in Figure 3.

Another solution is to strike a balance between available gain and noise figure, aiming to match the noise as little as possible, and adopt a design solution that takes gain into consideration. In this case, the transistor gain is about 15 dB and Fmin is about 0.7 (see Figure 3). This is the second solution mentioned in this article.

Figure 3: The family of available gain circles and noise figure circles on the same Ts plane.

2 Simulation of the design scheme with the best noise figure as the target

2.1 Input matching circuit design

For low noise amplifiers, in order to obtain the minimum noise figure, Ts has an optimal Topt coefficient value, at which the LNA reaches the minimum noise figure, that is, the best noise matching state. When the matching state deviates from the optimal position, the noise figure of the LNA will increase. In the previous qualitative analysis, Topt = 0.329∠125.99° and the corresponding Zopt = 30.007 +j17.754 Ω have been obtained. Next, the Passive CIRcuit / MicroSTrip Connector Window tool of ADS can be used to automatically generate the matching circuit of the input port.

Add a DA_SSMatch1 smart module to the schematic diagram, and then modify the settings: F = 2.1 GHz, Zin = 50Ω. It is worth noting that when using this tool to generate a matching circuit, Zload is the conjugate of Zopt. After the settings are completed, add an MSub control, which is mainly used to describe the basic information of the substrate. Modify the settings to H = 0.8 mm, Er = 4.3, Mur = 1, CONd = 5.88 × 107, Hu = 1.0e+ 33 mm, T = 0.03 mil. After the settings are completed, the automatic matching circuit can be generated, and the resulting circuit is shown in Figure 4.

Figure 4 Matching circuit of input port

After adding the input matching circuit to Figure 1, the S parameter simulation is performed. It can be seen that the position of the best noise coefficient Topt is successfully matched to the position of 50Ω due to the addition of the input matching circuit.

2.2 Output matching circuit design

The output matching circuit is designed according to the maximum power gain principle (taking into account the influence of the output stabilization circuit on the output impedance, the stabilization circuit should be taken into account when measuring the output impedance), that is, the output impedance (Zout = 8.055-j8.980, as shown in Figure 5) is matched to 50 Ω using the above method. The obtained output matching circuit is shown in Figure 6.

Figure 5 Output impedance matching

Figure 6 Output matching circuit

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2.3 Simulation results

Observing the final simulation results, we can see that the gain is 14.4 dB and the noise figure is 0.586, which is very close to the optimal noise figure of the transistor after stabilization of 0.573, and the gain flatness is low, and the stability performance is excellent. The specific performance indicators are shown in Figure 7.

Figure 7 Schematic diagram simulation data

3. Simulation of the design scheme with noise coefficient as the main consideration and gain as the consideration

3.1 Input matching circuit design

If the substrate material is epoxy glass FR4 substrate, the dielectric constant is 4.3, and the thickness is 0.8 mm, the transistor input impedance at 2.1 GHz is 16.827-j16.041. Using the above matching circuit generation method, the input matching circuit is designed using the single-branch module in the A DS design wizard. The matching circuit in Figure 8 can be quickly obtained. As shown in Figure 9, m6 = 50 (0.927+ j0.001). It is very close to 50Ω, so the input matching condition is relatively reasonable.

Figure 8 Input matching circuit

Figure 9 Original image of S11 after adding input matching circuit

3.2 Output matching circuit design

After completing the input matching circuit design, the output matching circuit can be designed. Here, the advantages of CAD software are fully utilized and the optimization method is used to achieve it. The basic process is as follows:

Add the input matching circuit results to Figure 10 and add the microstrip as shown at the transistor output. Bring up the optimization controls and set the optimization targets to -20 dB(S(11)) and -15 dB(S(22)).

At the beginning of the optimization, the width of T L1, T L2, and TL3 is set to 61.394 mil to ensure that the characteristic impedance of the microstrip line is 50 Ω, taking into account factors such as the board material and the board thickness. Preset the length of T L1, T L2, and TL3. After optimizing once, refresh the results and observe whether the indicators of various charts are better and whether the values ​​have reached the set maximum values. If they have reached the maximum values, change the settings again and optimize again. After repeated attempts, these values ​​will be changed again. If the changes have little effect on various indicators, you can try to change the values ​​of the resistors and input matching and optimize again.

After multiple debugging, it is found that the gain, noise factor and input-output standing wave ratio are better when R1 is set to 15Ω and TL7 is added. The simulation circuit schematic and optimization controls and target controls are shown in Figure 10.

Figure 10 Simulation circuit schematic diagram and optimization controls and target controls

3.3 Simulation results

By observing the final simulation results, we can see that the gain is 15.816 dB and the noise figure is 0.708, both of which are better than those in the qualitative analysis. Other performance indicators are shown in Figure 11.

Figure 11 Schematic diagram simulation data

4 Conclusion

By qualitatively analyzing the transistor, the design scheme of the low-noise preamplifier can be selected according to actual needs. The best noise coefficient of the first scheme is obtained at the expense of gain; the second scheme is obtained at the expense of improving the noise coefficient and reducing the value of the standing wave ratio VSWR. Both methods can be quickly implemented using computer-aided design tools, and each has its own value, which has been applied in many occasions.