Summary: BU8874/UB8874F is a DTMF telephone voice responder produced by ROHM Company. Its biggest feature is that it has a wide dynamic range and can convert 16 different DTMF signals into 4-bit binary serial data. This article introduces the main features, module structure, functional parameters and design methods of BU8874/BU8874F. Finally, its typical application circuit is given.
Keywords: Telephone answering machine DTMF BU8874/BU8874F
1 Overview
DTMF telephone voice receiver integrated circuit BU8874/BU8874F is a first-class telephone voice responder produced by ROMHM Company. They can convert 16 different DTMF signals into 4-bit binary serial data. Among them, BU8874 uses an 8-pin DIP package, while BU8874F uses an 18-pin package. The internal circuit structures of the two chips are basically the same. The biggest feature of this device is its wide dynamic range, which eliminates the need for an amplifier to extend the input dynamic range. In addition, BU8874/BU8874F is designed using specialized digital technology, so timing control can be reliably performed by the main controller. BU8874/BU8874F can be widely used in DTMF telephone voice responders.
The main features of BU8874/BU8874F are as follows:
●Has a wide dynamic range of 45dB;
●With low point source mode;
●Adopt 4-bit binary code serial output;
●The BU8874/BU8874F can be reliably timed and controlled through the main controller;
●With input delay response pin (ACK pin);
●Can use 4.19MHz crystal buzzer.
2 Structural functions and main parameters
2.1 Internal structure and pin functions
BU8874/BU8874F are packaged in DIP-8 and SOP-18 respectively. Figure 1 shows the internal structure and pin arrangement of BU8874/BU8874. The functions of each pin of BU8874/BU8874F are listed in Table 1.
Table 1 Pin functions of BU8874/BU8874F
BU8874 pin number | BU8874F pin number | Pin name | Function Description |
1 | 2 | INPUT | Audio signal input terminal, there should be a coupler in front of this port |
2 | 5 | PWDN | Sleep signal input pin. When this pin is low level "L", the device is in normal operating mode. When this pin is high level "H", the device enters a low-power sleep state. It should be noted that when setting the PWDN pin to high level "H", the ACK pin should first be set to low level "L". |
3 | 6 | OSC | Device internal oscillator input pin. A 4.194304MHz crystal oscillator or other suitable external oscillator should be connected between this pin and the GND pin. |
4 | 8 | GND | Ground pin |
5 | 11 | SD | Serial data input pin. When the EST pin is high, if a serial pulse is input at the ACK terminal, a 4-bit binary code signal will be output at the SD terminal. |
6 | 13 | ACK | Response pulse signal input pin. There is a certain delay in this pin. When the EST pin enters the high level, the pin will activate the SD data output pin to output a 4-bit DTMF digital signal under the action of four consecutive pulses, and the rising edge of the first pulse will be used when the data is shifted. lock |
7 | 14 | EST | Control signal output pin. When a valid DTMF signal arrives, this pin enters high level |
8 | 17 | VDD | Power terminal |
2.2 Main parameters
The power supply operating voltage of BU8874/BU8874F should be in the range of 4.75~5.25V. The oscillator frequency of the external crystal (can also be ceramic) resonator between their 3-pin OSC and GND should be selected as 4.194304MHz, and its accuracy should be within Within ±0.1%. The following are some main limit parameters of BU8874/BU8874F:
●Maximum power supply voltage VDD: 7V;
●Maximum input voltage range: GND-0.3V~VDD-0.3;
●Maximum output voltage range: GND-0.3V~VDD-0.3;
●Maximum power consumption: BU8874 is 500mW;
BU8874F is 55mW;
●Working temperature range: -10~+70℃;
●Storage temperature range: -55~125℃.
3 Working principle
3.1 Normal operation
When a DTMF signal is input to the INPUT pin of BU8874/BU8874F, a pair of band-pass filters in BU8874/BU8874F will convert the DTMF signal into high-frequency (COL) and low-frequency (ROW) audio signals respectively. At the same time The two audio signals are converted into digital signals and sent to the digital detector (DIGITAL DETECTOR). The digital detector detects the two tone signals to determine whether they are valid signals of DTMF. If they are valid signals of DTMF, then the digital detector of BU8874/BU8874F will send a DETECT signal to its control circuit, and also send a corresponding COLUMN and ROW address signal to the code converter (CCDE CONVERTER). At this time, the transcoder also outputs an enable (ENABLE) signal to the control circuit of the device after encoding the received and detected DTMF signal.
Under the combined action of the DETECT signal output by the digital detection circuit and the ENABLE signal output by the code conversion circuit, the control operation circuit in BU8874/BU8874F will output an initial control operation signal. At this time, if the EST pin enters a high level, then Indicates that the device has detected a valid DTMF signal.
When the EST pin is high, if a serial pulse signal is input to the ACK pin, then the SD pin will output a binary DTMF decoded signal. Figure 2 shows the operation timing diagram of the above three pins.
If a parallel pulse sequence is input to the ACK pin, the data will be latched on the rising edge of the first pulse of the parallel/serial converter (PARALLEL-SERIAL CONVERTER), and its lowest bit LSB will be output by the SD pin at the same time . After this, in the parallel pulse input by the ACK pin, each bit of each pulse will be output by the SD pin until the remaining three bits in the data are output. At this point, all four data bits in the four pulses will be output. Its operation sequence is shown in Figure 3.
If the number of pulse sequences input to the ACK pin is only three or less, then the subsequent DTMF input will not be fully decoded; and if the number of pulses input to the ACK pin exceeds four, the system will not Accepted without functioning properly until the EST pin is high again. Table 2 shows the serial data format output from the SD terminal.
Table 2 Data output format of SD port
ROW(Hz) | COL(Hz) | No. | b3(MSB) | b2 | b1 | b0(LSB) |
697 | 1209 | 1 | 0 | 0 | 0 | 1 |
697 | 1336 | 2 | 0 | 0 | 1 | 0 |
697 | 1477 | 3 | 0 | 0 | 1 | 1 |
770 | 1209 | 4 | 0 | 1 | 0 | 0 |
770 | 1336 | 5 | 0 | 1 | 0 | 1 |
770 | 1477 | 6 | 0 | 1 | 1 | 0 |
852 | 1209 | 7 | 0 | 1 | 1 | 1 |
852 | 1336 | 8 | 1 | 0 | 0 | 0 |
852 | 1447 | 9 | 1 | 0 | 0 | 1 |
941 | 1336 | 0 | 1 | 0 | 1 | 0 |
941 | 1209 | * | 1 | 0 | 1 | 1 |
941 | 1477 | # | 1 | 1 | 0 | 0 |
697 | 1633 | A | 1 | 1 | 0 | 1 |
770 | 1633 | B | 1 | 1 | 1 | 0 |
852 | 1633 | C | 1 | 1 | 1 | 1 |
941 | 1633 | D | 0 | 0 | 0 | 0 |
Table 3 Input logic selection for operating modes
ACK | PWDN | ACK PWDN status |
X | L | Normal operating mode |
L | H | low power mode |
H | H | undefined |
3.2 Low power consumption mode
If ACK is low, then the low power consumption mode of BU8874/BU8874F will be activated on the rising edge of PWDN. Table 3 lists the operation mode input logic selection methods of BU8874/BU8874F. When the circuit is in low power mode, the ACK pin can be moved from low level to high level and back to low level again. When PWDN is low, the circuit will return to normal operating mode. After the circuit switches from the low power mode to the normal operation mode, if there is still a valid DTMF signal, that is, the valid input signal of the circuit in the low power mode still exists, then the data will be generated by the input ACK pulse sequence. A second read-in is performed (the first read-in has been missed with the resumption of normal operating mode). In fact, if the circuit enters the low-power mode n times, as long as the input DTMF signal continues to exist, then when EST is high, the data will be re-read n+1 times.
4 application circuit
BU8874/BU8874F are ideal devices for voice transponders in DTMF circuits. Its application circuit is very simple. Figure 4 is a typical application circuit of BU8874/BU8874F. In the figure, the main function of the preamplifier composed of transistor 2SC1740, resistors R591 ~ R595, and capacitors C592 ~ C593 is to increase the receiving sensitivity of DTMF signals. If you want to input the DTMF signal directly to BU8874/BU8874F, you can short-circuit JP592 in the picture. The selection principle of coupling circuit C501 is that it should be able to couple DTMF signals above 697Hz well. Because the BU8874/BU8874F device has high requirements for the oscillation frequency accuracy of its crystal oscillator. Therefore, when designing, you should try to choose a quartz crystal oscillator with higher frequency accuracy. If you choose a ceramic oscillator, you must ensure that its accuracy is within ±0.1%. As for the bypass capacitor connected to VCC, a 100μF ordinary aluminum electrolytic capacitor can be used.
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