New architecture in the post-Moore era: storage and computing integration

Recently, the "post-Moore era" technology in the field of integrated circuits has attracted widespread attention. As a major development direction of the "post-Moore era", "storage and computing integration" is expected to solve the "storage wall" and "power consumption wall" problems faced by current integrated circuit systems, and has important strategic value.

The so-called "storage and computing integration" refers to the transformation of the traditional computing-centric architecture into a data-centric architecture, directly using memory for data processing, thereby integrating data storage and computing in the same chip, greatly improving computing parallelism and energy efficiency, and is particularly suitable for the field of deep learning neural networks, such as wearable devices, mobile devices, smart homes and other scenarios.

The key to "storage and computing in one" lies in breaking through the bottleneck of data transmission rate and power consumption between memory and processor through data bus, which is separated from data storage and data processing under the traditional von Neumann computing architecture. In terms of speed, the limited bandwidth of the data bus seriously restricts the performance and efficiency of the processor. AI computing requires a computing rate of 1PB/s, while the speed of SRAM as a cache is only 100TB/s, and the speed of main memory DRAM is only 1TB/s. A "storage wall" is formed between each level of storage, which restricts the overall computing rate of the system. In terms of power consumption, the frequent migration of data between memory and processor brings serious transmission power consumption problems. In the era of Moore's Law, this power consumption can still be reduced proportionally with the reduction of transistor size, which is called "Denard miniaturization". However, when the characteristic size of the chip in the "post-Moore era" enters 7nm, the leakage caused by quantum effects causes the unit power consumption density to rise rapidly. The static power consumption caused by data transmission has become more and more a constraint on chip development, forming a "power consumption wall". The design of chips can no longer rely on size miniaturization to achieve better performance and energy efficiency, and the "storage and computing in one" architecture has begun to show its unique advantages.

The concept of integrated storage and computing can be traced back to the 1970s. Kautz et al. of Stanford Research Institute proposed the concept of integrated storage and computing in 1969, hoping to directly use memory to perform some simple computing functions and reduce the movement of data between processors and memory. Since 2010, with the continuous increase in data volume and the emergence of technologies such as 3D memory, the concept of integrated storage and computing has regained widespread attention and has begun to be applied to commercial-grade DRAM main memory. Especially since 2015, with the rise of big data applications such as cloud computing, the Internet of Things, and artificial intelligence, integrated storage and computing has been widely studied and applied by academic and industrial circles at home and abroad. At the 2017 Microprocessor Annual Conference (Micro 2017), including NVIDIA, Intel, Microsoft, Samsung and the University of California, Santa Barbara, all launched their prototypes of integrated storage and computing systems.

The performance and power consumption advantages of integrated storage and computing have been initially proven. Samsung first released the HBM-PIM processor based on high-bandwidth memory (HBM) technology at the International Solid-State Circuits Conference (ISSCC) held on February 22, 2021. Samsung pointed out that when they tested the new technology with the existing HBM2 Aquabolt system, the system performance doubled and energy consumption was reduced by 70%.

In the context of this initial change, in order to support the high-quality development of my country's integrated circuit industry in the "post-Moore era", the China Center for Information Industry Development will hold the 2021 16th 'China Core' Integrated Circuit Industry Promotion Conference in Zhuhai, Guangdong from October 28 to 29, 2021. The conference will continue the activity purpose of "establishing a business by use and developing a business by use" in the past 15 years, and will be held with the theme of "China Core on the Chain Achieves Made in China". At the same time, there will be a ceremony to announce the results of the "China Core" excellent product collection, a special summit forum, and a city integrated circuit industry development display. Looking forward to your arrival!