The final step before successful tape-out: How to optimize and improve chip verification

A tiny chip integrates billions or even tens of billions of transistors in a space the size of a fingernail, which can be said to be the result of the highest wisdom of mankind. With the evolution of process technology, the transistors integrated in the same unit area are becoming more and more dense. The details of TSMC's 3nm process revealed in early April this year showed that 250 million transistors were integrated per square millimeter, which is an astonishing density.

The birth of such a sophisticated and complex chip not only requires the "refining" of countless processes, but also involves R&D costs and wafer production costs that are as high as hundreds of millions of US dollars. This means that no errors are allowed in every aspect of chip design.

Data shows that the success rate of chip re-spinning is only about 35%, and the main reason for repeated chip re-spinning is insufficient verification. It is understood that the resources required for chip design verification account for 60% to 80% of the entire design resources.

Verification is the last guarantee for chip front-end development. It is an important cornerstone to ensure the success of the first version of the chip and a key link to enter the market. As the content and complexity of the chip increase day by day, the space and scope that verification needs to explore are getting larger and larger. Each verification is like "finding a needle in a haystack", so the time required for verification is also getting longer and longer.

The completion of physical layout verification represents the completion of the entire chip design stage. Its importance is self-evident, especially with the high integration and complexity of integrated circuits, layout verification is even more important. Layout verification ensures that the chip is accurately implemented according to its design functions, mainly including design rule checking (DRC), layout comparison checking (LVS), circuit extraction (NE) of the layout, electrical rule checking (ERC) and parasitic parameter extraction (PEX).

However, traditional verification tools can either verify the geometry of the layout or the electrical characteristics of the circuit, but cannot perform both verifications at the same time. In order to make the verification work more efficient and optimized, is there a verification tool that can take into account both verifications?

The above-mentioned demand is the background for the birth of context-aware physical verification (PV). It is understood that context-aware PV checking was originally an extension of basic design rule checking (DRC), but after rapid development, it can now be used to meet the stringent process and reliability requirements of today's designs. Context-aware physical verification combines the electrical characteristics of components with their physical layout and analyzes this information to evaluate various design conditions, from high-level design rule compliance to circuit and reliability verification, to design optimization and completion.

In addition to DRC, context-aware verification adds a new dimension to other verification flows. As process nodes evolve, layouts become smaller, packaging becomes tighter, and design/application requirements become more complex in terms of the number, complexity, and variability of voltage domains, nets, and patterns, the challenges of context-aware verification flows grow. For example, instead of defining critical layout patterns based solely on optical proximity correction (OPC) hotspots or silicon failures, context-aware flows can also expand the pattern library to include electrically driven patterns such as differential pairs, current mirrors, silicon photonic structures, and others.

In the above scenario, invoking context-aware checks without automatic support requires designers to manually analyze and select electrical components, cross-reference between the front-end/back-end, and manually add markup layers and layout annotations, which is not only time-consuming and labor-intensive but also prone to human error. Given the growing number and types of context-aware checks, manual methods are no longer feasible.

In addition, as more complex products are developed and consumers have higher and higher requirements for performance and reliability, the use of automatically executed context-aware checks has become an indispensable best practice for providing reliable and timely products to the market. As a result, the market is in urgent need of a verification platform that can automatically perform context-awareness. It is reported that the Calibre platform launched by Mentor, an internationally renowned EDA manufacturer, can perfectly solve the above problems. How is it achieved specifically? Download the document to view the original solution.