MG3500 System-on-Chip Supporting H.264 HD Codec

1 Introduction

Consumer and industrial H.264 encoders require the best video quality even with limited storage capacity or limited bandwidth. Therefore, a system-on-chip MG3500 application design supporting H.264 HD encoder is presented here, which is very versatile for HD video codec related applications.

2 Introduction to MG3500 SoC

MG3500 SoC (System-on-chip) is a H.264 HD codec system-on-chip launched by Mobilygen. It integrates an embedded ARM9 processor, NAND/NOR flash memory, SD/SDIO/MMC/CE-ATA interface, 10/100/Gigabit Ethernet MAC and USB2.0 OTG port, as well as AES/SHA encryption algorithm based on reliable Internet, UART, JTAG, serial control and general I/O. The 240 MHz ARM9 processor includes DSP extension and 16 KB of instruction cache, data cache and temporary storage memory.

MG3500 SoC supports H.264 basic profile, main profile and high-definition quality up to level 4.1. Macroblock adaptive field/frame (MBAFF) encoding in main profile and high-definition quality allows the highest quality per bit of interlaced material. It also supports integrated circuit device (IDE) and compact flash memory. 2.1 Main Features of MG3500 SoC (1) HD H.264 Codec Dual-stream HD/SD H.264 codec, supports H.264 basic profile, main profile and high-definition, H.264 codec resolution up to 1 920×1 080 i, programmable resolution and frame rate, multi-stream SD codec, video bit rate range: 64 Kb/s to 62.5 Mb/s, macroblock adaptive field/frame (MBAFF). (2) MPEG-2 Decoder HD/SD decoder converts HD MPEG-2 stream to H.264 format in real time, multi-stream SD MPEG-2 decoding. (3) JPEG/MJPEG Codec JPEG codec, HD/SD MJPEG, supports Exchangeable Image File Format (EXIF). (4) Audio Codecs High-fidelity dual-channel AAC-LC codec, MP2 format codec, MP1 and MP3 format decoders, Dolby Digital 5.1 channel decoding, G.711 codec, adjustable bit rate and sampling frequency, support for codec expansion, 1-way SONY/PHILIPS home digital audio output interface (S/PDIF) or 2-way I2S audio I/O ports. (5) Video Input Processor (VIP) Adjustable video direct input, 2 ITU-R BT.1120 parallel interfaces, 4 ITU-R BT.656 parallel interfaces, 2 advanced video input processors, support for digital image stabilization, support for smooth digital zoom. (6) Video output processor (VOP) can support ITU-R BT.1120 or ITU-R BT.656 HD/SD output, multi-stream decoding supports picture-in-picture and multi-channel mixed video output, 18-bit or 8-bit RGB format LCD interface, high-quality video compression output, 2 overlay layers with alpha blending and cursor, and generate selectable external synchronization signals. (7) Built-in ARM926-EJ processor 240 MHz general-purpose processor, 16 KB data cache memory, 16 KB instruction cache memory, 16 KB temporary memory. (8) System connectivity 1 10/100/Gigabit Ethernet MAC, 1 USB2.0 OTG port, high-speed bitstream I/O port, AES/SHA encryption. (9) Peripheral device interface supports SD/SDIO/MMC/CE-ATA interface, supports IDE and Compact Flash (10) General interface 2 SPI or two-bus serial communication interfaces, 3 UART interfaces, 3 pulse width modulators, 8 dedicated GPIOs. It can be expanded to 72 GPIOs. (11) The system core voltage is 1.0 V ± 10%, the SDRAM voltage is 1.8 V ± 10%, the I/O port voltage is 1.8 V, 2.5 V, 3.3 V ± 10%, and the single crystal drives the audio/video phase-locked loop. (12) Power consumption (MG3500 + SDRAM) H.264 HD 30fps + AAC encoding 750 mW. 2.2 Interfaces of MG3500 SoC Figure 1 shows the functional block diagram of MG3500 SoC. MG3500 SoC has 2 video input processors (VIP), 1 video output processor (VOP), 1 video multimedia engine (MME) and 1 audio multimedia engine. Two identical VIPs can perform high-quality video scaling, chroma and gamma adjustment, filtering, and extraction video analysis operations, and can process two independent video inputs with a maximum resolution of 1 920×1 080 i; VOP supports high-quality video compression output, 2 graphics memory areas, 1 hardware cursor, supports chroma and gamma adjustment and can output full TV signals. Each graphics memory area is 1 to 32 bits: Video MME is a proprietary reduced instruction set computer (RISC) optimized for single-cycle context switching and low power consumption, controlling VIP, VOP and video core.

2.2.1 Video Interface

Two 8-bit video input interfaces support independent ITU-R BT.656 inputs, and each video input supports independent clock and synchronization signals. Supports standard definition input, and setting the clock frequency above 100 MHz can also support non-standard video signals including 8-bit video signals from high-definition sensors. The two 8-bit video input interfaces can also be combined into a 16-bit ITU-R BT 1120 high-definition input interface. The operating modes supported by the MG3500 SoC are listed in Table 1.

2.2.2 Audio Interface
The audio multimedia engine of MG3500 SoC can make all audio codecs effective. The audio interface includes 2 I2S inputs and 3 I2S outputs. One of the I2S inputs is connected to the audio clock, and the other I2S input and 3 I2S outputs are connected to another clock. One of the audio output ports can also be used to generate S/PDIF compatible audio. 2.2.3 Ethernet Port, USB Port and SD/MMC Interface The Ethernet Media Access Controller (MAC) of MG3500 SoC supports 10/100/Gigabit Ethernet through a Media Independent Interface (MII), Reduced Media Independent Interface (RMII) or Gigabit Media Independent Interface (GMII). MG3500SoC can also be directly connected to an Ethernet switch that supports RevMII interface. The USB interface supports high-speed USB 2.0 OTG and can be a master or slave device. The SD/MMC interface is used to support SD/SDIO/MMC/CE-ATA devices. The clock frequency of this 4-bit interface can reach 50 MHz. 2.2.4 HOST Interface The MG3500 SoC can work in both master and slave modes. When the MG3500 SoC works in master mode, the signal lines of the HOST interface are used to connect NOR Flash, NAND Flash, COMPACT Flash, IDE and other external devices. Serial ports and other I/O ports. The MG3500 SoC contains multiple UARTs for communication, pulse width modulators (PWM) for control, two-bus serial communication interfaces (TWI) and serial peripheral ports (SPI) for peripheral control. The 8 dedicated general purpose I/O ports (GPIO) of the MG3500 SoC and the other 64 multiplexed GPIOs can be used for system control. These multiplexed GPIO pins have many different uses, and the GPIO function can only be used when the main function of the pin is not used.

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3 Typical Applications The typical application of MG3500 is vehicle-mounted DVR, because it has the highest quality high-definition (HD) H.264 encoding/decoding for processing multiple standard definition (SD) data streams, and also provides extensive network support for transmitting secure video data streams over IP networks; typically, an en-ViE codec requires only 500mW of power consumption for 108li encoding, which is only one-tenth of the power consumption of DSP-based solutions. Figure 2 is a functional block diagram of the mainboard module of the vehicle-mounted DVR, which includes a linear power supply circuit, CPU, SDRAM, reset circuit, Flash storage module and FPGA logic circuit.

Transform TW2864 non-standard I2S to standard I2S, provide 1-channel I2S as network intercom, merge data stream with audio input and input to MG3500, audio and video input and output, audio and video encoding uses TW2864, audio decoding uses TW2864, video decoding uses ADV7393, serial port expansion circuit, peripheral RS232, RS422, USB, 1-channel Ethernet, switch signal detection and output control circuit, alarm input and output, working status indication. SB is expanded through USB HUB, and device status indication, alarm input and output, switch detection, and CAN are completed by ARM7.

The vehicle DVR converts 4-channel analog vehicle audio and video signals into digital signals in BT.656 format through a dedicated A/D converter, and the processor compresses the data into H.264 format data and stores it in the hard disk. It has a fast and convenient query playback mode, a high-speed USB2.0 interface, and a broadband network interface for convenient data backup. At the same time, combined with the particularity of the vehicle industry, other functions such as film and television playback and car black box can be expanded.

The functional block diagram of the vehicle-mounted DVR hardware consists of a power board module, an audio and video encoding module, an audio and video decoding module, a data storage module, an external interface module, an I/O acquisition module, etc.

The power board module provides a reliable and stable power supply for the system, provides overvoltage and overcurrent protection; common mode and differential mode interference filtering, etc.; and outputs 12 V and 5 V voltage signals.

The audio and video encoding module is the focus of the system design. TW2864 implements 4-channel audio and 4-channel video encoding. Due to the limitation of the number of MG3500 video capture ports, the 4-channel 27 MHz BT.656 format video streams output from TW2864 are converted into 2-channel 54 MHz video streams after passing through the DDRIIRAM cache connected to the FPGA and input to the video capture port of MG3500 for processing by MG3500. After TW2864 converts the input 4-channel analog audio signals into digital signals, they are input to MG3500 through an I2S port for processing.

The audio and video decoding module realizes the real-time preview and image revisiting functions of the image. The video decoder converts the digital signal output by the CPU into an analog video signal that can be transmitted remotely.

The data storage module mainly includes two parts: a hard disk and an SD card, which realize local storage of audio and video data. Important alarm data, such as dual backup of the hard disk and the SD card. At the same time, the SD card can also be used for program updates, log storage, data reading and other functions.

The external interface modules mainly include USB2.0 High Speed, Ethernet, RS485, RS232, etc. Among them, USB realizes data transfer, mouse and other USB devices; the Ethernet interface realizes data network backup, network parameter setting, video network preview and other functions; RS485 is used for external PTZ; the RS232 interface is connected to external GPRS/CDMA modules, and can also connect other RS232 devices. The I/O acquisition control module realizes the collection of alarm quantity, the output of external alarm quantity, the vehicle status collection, and the equipment status indication.

Issues that should be noted: USB speed is the bottleneck of this part. Mobilygen does not support users to use expansion devices to expand the USB port, so USB HUB is used. The CAN interface device uses ARM7LPC2109 with CAN interface. If 2 channels are used, LPC2119 can be used. Since the SPI port is occupied and the number of MG3500's GPIOs is insufficient, the alarm, vehicle status collection, and CAN are completed by an ARM7. The MG3500 IDE interface only supports 128G hard drives, so only a USB to SATA bridge can be used.

4 Conclusion
Mobilygen's MG3500 SoC is capable of handling the highest quality HD H.264 codec for multiple standard definition data streams, while also providing extensive network support for transmitting secure video data streams over IP networks, and also includes an MPEG-2 decoder and a JPEG codec that supports Motion JPEG format. At the same time, some consumer and industrial applications of H.264 codecs require the best video quality even with limited storage capacity or limited bandwidth. Therefore, in these application areas, MG3500SoC will surely have a wide range of application prospects.