Image acquisition and processing system based on ADSP-TS201S-EEWORLD

Collect

introduction

With the continuous improvement of people's requirements for real-time signal processing and the rapid development of large-scale integrated circuits, digital signal processor DSP chips, which are the core and symbol of digital signal processing, have been rapidly developed and applied. It can be widely used in real-time signal processing fields such as communication systems, graphics/image processing, radar sonar, and medical signal processing. As far as ADI is concerned, following the 16-bit fixed-point ADSP21xx and 32-bit floating point ADSP21xxx series, it has recently launched a new device in the TigerSHARC series. This article introduces the design of an image acquisition and processing system using the ADSP-TS201S chip in this series.

Overall system plan

The system can complete image collection, processing and display, thereby realizing intelligent signal processing for target recognition and tracking. This system collects digital and analog video data from the camera, and displays it on the PC through the PCI bus after processing. The entire system mainly consists of three parts: video signal acquisition module, DSP image processing module, and PCI interface module (Figure 1).

Figure 1 Block diagram of image acquisition and processing system

Circuit design of each functional module of the system

·Video signal acquisition module

The camera provides two video signals: one analog video and one digital video.

After the analog video signal is clamped, corrected and amplified, the signal is sent to the A/D converter, and then the video signal is latched by the FPGA and sent to DSP1; through the video synchronization separation circuit, the LM1881 separates the analog video lines and Field synchronization signal is used to control the acquisition of video data to DSP1 for image processing. The clamp correction and video synchronization circuit is shown in Figure 2. The analog video is input through the op amp, and the center level is adjusted to 3.3V and added to the A/D input. The A/D converted data enters the FPGA latch. The op amps all use ADI's AD8047AR, and the A/D converters use ADI's AD9050. AD9050 is a 10-bit A/D converter, and the upper 8 bits are entered into the FPGA. The sampling clock is 12MHz, which is the same as the digital video signal. It is generated by FPGA dividing the 48MHz clock by four.

Figure 2 Analog video input conversion circuit

The digital video signal of the camera is 14 pairs of differential signals. The differential signals are converted into single-ended signals by the FPGA and the data is latched. 14 bits per pixel, 320×240 per frame.

The FPGA uses ALTERA's CYCLONE series EP1C3T144C-6, and the configuration chip uses EPC2LC20. EP1C3T144C-6 has a dedicated I/O port for converting differential signals to single-ended signals. The digital and analog video signals latched in the FPGA are output to the DSP1 data bus according to the working mode selection, and are read and processed by DSP1. The data rate is the same as the sampling rate of analog video and the data rate of digital video. Working mode selection and switch control are introduced to FPGA through PIC9054.

·DSP processor module

The DSP processor array module mainly consists of four high-speed and high-performance DSP processing chips ADSP-TS201S to form a multi-DSP processor system. The performance of ADSP-TS201S is as follows:

The basic performance indicators are as follows:

When running at 600MHz, the core instruction cycle is 1.67ns

24M bits on-chip DRAM, divided into 6 4M bits blocks (128K words X 32 bits)

On-chip dual arithmetic modules, each containing an ALU, a multiplier, a shifter and a register bank

Double integer ALU provides data addressing and pointer operation functions

On-chip provides 14-channel DMA, external port, 4 link ports, SDRAM controller, programmable flag pin, and 2 timers

On-chip arbitration system enables seamless connection of 8 TigerSHARC DSPs

3 internal independent 128-bit buses

External data bus 64 bits, address bus 32 bits

4.8 billion 40-bit wide MAC operations per second or 1.2 billion 80-bit wide MAC operations per second; 1024-point complex FFT (base 2) time 15.7us

External port 1G bytes per second; link port (each) 1G bytes per second

DSP1 in the DSP processor array module is used to sort out the collected video signals, perform corresponding preprocessing, and then distribute the data to the subsequent DSP for further processing.

The DSP1 parallel port should be connected to the video data output by the FPGA, and also connected to FLASH to complete DSP loading. IRQ0 and IRQ1 of DSP1 are used as frame interrupt and line interrupt of video input respectively, and are connected to FPGA. The connection circuit is shown in Figure 3 below.

FLASH uses AMD's AM29LV017D, which is a 2M x 8-Bit memory. FLASH can be programmed through DSP1. It is necessary to ensure that when reading and writing FLASH, the data output bus D0~D13 of FPGA is high impedance. On the contrary, when the data channel is running, , the FLASH output should also be made high impedance, so use BMS to select FLASH.

Figure 3 DSP1, FPGA, FLASH connection diagram

DSP2 and DSP3 in the DSP processor array module are used to implement the main algorithms in image processing. DSP2 and DSP3 use link ports to connect to DSP1 respectively to receive the data transmitted from DSP1. DSP2 and DSP3 also use link ports to connect to DSP4 respectively, and transmit the processed data to DSP4 through the link port for the next step of processing and data processing. tidy. In addition, DSP2 and DSP3 are also directly connected using link ports to realize the channel between DSP2 and DSP3, so that DSP2 and DSP3 can be easily configured into pipeline or parallel processing modes.

DSP4 in the DSP processor array module receives the data sent by DSP2 and DSP3. After further processing, the final processed data is sent to the dual-port RAM through the data bus, and the data is sent to the PC through the PCI interface chip PCI9054. This dual-port RAM uses three pieces of IDT70LV27 (32K x 16-Bit) to form a 96K After a frame of image data is filled, an interrupt is generated to the PC and the PC is requested to read the data. When the PC finishes reading a frame of image data, it should provide a corresponding response to allow DSP4 to refresh the dual-port RAM. The DSP array machine interconnection circuit is shown in Figure 1, and the connection between DSP4 and dual-port RAM is shown in Figure 4. DSP4 is connected to three pieces of dual-port RAM to form an interface with PCI9054. FLAG0 of DSP4 serves as the video transmission handshake signal output through PCI9054.

The ADSP-TS201S array machine adopts the link port interconnection method, and sets the data transmission start FLAG signal in the main data transmission direction to generate an interrupt on the receiver's IRQ to better achieve timing matching.

DSP1 introduces the work/off selection (FLAG1 input), and the data mode (digital/analog) selection is read in by the DATA14 pin. When a frame of data starts to be input, the data selection mode can be read once, and then it can no longer be processed. .

Figure 4 DSP4 and dual-port RAM interface

·PCI interface module

The PCI interface adopts PLX's PCI9054 interface chip, 32-bit, 33MHZ data bus. Three pieces of dual-port RAM (IDT70LV27) RAM1, 2, and 3 are used as DSP4 data output buffer. Read into PC by PCI9054. In the dual-port RAM, it is equivalent to the right half of the interface. The circuit connection of PCI9054 is shown in Figure 5. PCI9054 corresponds to the signal of the PCI slot, connect according to the PCI slot name, and select 93CS66 to load the EEPROM. Introducing LD0~LD3 into the FPGA can output 4-bit status in a single I/O write mode for host control. On and off, digital video/analog video selection uses one of the decoders of A16~17 as the address selection. After FPGA reads it in, it decodes it into a control signal and outputs it.

Figure 5 Connection between PCI9054 and dual-port RAM and FPGA

Conclusion

The image acquisition and processing system based on ADSP-TS201S can complete high-speed image processing, realize real-time display of images, and target tracking. In practical applications, the system works stably and achieves the expected results.

Keywords：bus Reference address：Image acquisition and processing system based on ADSP-TS201S

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