DSP peripheral memory marching test technology based on navigation receiver

DSP peripheral memory marching test technology based on navigation receiver

DSP is the core of digital computing in electronic systems. The correctness of the data it operates is the basic guarantee for the normal operation of the system. Taking the DSP application in the navigation receiver as an example, real-time tasks such as capture and tracking, signal demodulation, message format conversion, multipath suppression, and anti-interference are interacting with bit information all the time. As a transit station for system data, any physical failure of the memory may cause serious abnormalities in the system. Therefore, a fast and effective memory test algorithm is needed to perform real-time functional verification and detection on the DSP peripheral memory to ensure that the device has no physical failures [1]. This method is specifically designed for the detection of AF, SAF, SOF, TF, and CF failures in the memory, as shown in the dotted box in Figure 1.

Among the existing fault detection algorithms, the test vectors of the Checkerboard algorithm are similar to the black and white checkerboards in chess. The test sequence with intervals of 0-1 is written into the memory. The running time is O(N), but the fault coverage is low[2]. The Galpat algorithm traverses the influence of each bit on other bits and can detect all non-linked static faults, but the running time is O(N2)[3]. Under the current process conditions, it takes hundreds of years to complete the Galpat test of a megabyte memory. The marching algorithm is a memory test algorithm commonly used in industry, such as MATS++, March X, March C-, etc.[4]. Its running time is O(N) and has a high fault coverage, but it usually cannot cover all static non-linked faults.

Based on the consideration of static non-link faults of memory, this paper takes words as the basic detection unit and proposes a progressive test scheme that can detect all SAF, TF, AF, SOF, and CF faults. The amount of calculation is (11N+5v)/u+2N, where each word is u bits and u=2v.

1 Fault Model and Definition

This paper adopts the common terminology definitions in reference [2].

1.1 Definition of terms

In order to facilitate the description of the fault detection method using words as the basic detection unit, the following terms are defined:

u: the number of bits in a word, u=2v (v is a non-negative integer).

· P: u-bit test vector word.

P0: All-0 test vector word. P0=bu…b2b1, bu=…=b2=b1=0.

· M: A bit-based march test algorithm consisting of a series of march sequences.

MP: M corresponds to the word-based marching test algorithm, P is a u-bit test vector word.

1.2 Memory Fault Model

Memory static non-link faults include single unit faults and coupling faults.

(1) Single unit failure

Single unit faults include: SAF, SOF, AF and TF, and their classification and detection sequence are shown in Table 1.

(2) Coupling failure

A coupling fault is when the logic value of a unit is affected by another unit. It includes: ①CFin fault (inversion coupling fault) means that the flip of unit i will cause the flip of unit j; ②CFid fault (idempotent coupling fault) means that the flip of unit i will cause the logic value of unit j to be a certain value (0 or 1); ③CFst fault (state coupling fault) means that when unit i is assigned a certain value, it will cause the logic value of unit j to be a certain value (0 or 1). The coupling fault list is shown in Table 2.

2 Word-based marching algorithm

2.1 Bit-based marching vs. word-based marching

The bit-based march traverses all bit units, while the word-based march traverses all word units. For an N-bit memory, the difference between the two marching methods is shown in Table 3.

Currently, most memory read and write operations are based on words. For an N-bit memory, if a word is u bits, then for the same marching sequence, the test time of word-based marching is reduced to 1/u of the original compared to bit-based marching; the disadvantage of word-based marching testing is that the fault detection rate will decrease, and more test vector words are needed to improve the fault detection rate.

2.2 Intra-word coupling faults and inter-word coupling faults

Coupling faults are divided into two types: intra-word coupling and inter-word coupling, as shown in Figure 2. Intra-word coupling faults refer to two bits i and j in the same word, where the state change or operation of bit i will cause a logic value fault in bit j; inter-word coupling faults refer to bits i and j being in two different words, where the state change or operation of bit i will cause a logic value fault in bit j.

As can be seen from FIG. 2 , if M can detect all CF faults, then MP0 can detect all inter-word coupling faults, but usually can only detect a portion of intra-word coupling faults.

[page]

2.3 Word-based fault detection

In order to detect all SAF, TF, AF, SOF, and CF faults, consider using words as the basic detection unit and use the following progress sequence for fault detection:

in:

The memory has a total of N bits, each word is u bits, u=2v.

P0=bu…b2b1, then bu=…=b2=b1=0

PAj=bu...b2b1, then when i mod 2j>2j-1, bi=1, i=1, 2,...,u.

PBj=bu…b2b1, then when i≤j, bj=1; when i>j, bi=0.

Conclusion 1: M0 can detect all SAF, TF, AF faults, and all <↑;→>, <↓;→>, <;←>, <↑;←>, <↓;←>, <;←>, <↑;>, <↓;>, <↑;1/0>, <↓;0/1>, <0;0/1>, <1;1/0> faults.

Proof: The bit-based marching algorithm corresponding to M0 is March C-. March C- can detect all SAF, TF, AF, CFin, CFst, and CFid[4], so M0 can detect all SAF, TF, AF, inter-word CFin, inter-word CFst, and inter-word CFid. Next, we examine M0's detection of CF faults in words.

Since M0 contains the marching sequence , it is possible to detect the <↓；0/1> and <0；0/1> faults caused by the coupled bits in the word flipping from 0 to 1. Since M0 undergoes two bit flipping operations of writing 0 , writing 1, and writing 0, it is possible to detect all unidirectional flip CFin faults (including <↑；→>, <↓；→>, < ；←>, <↑；←>, <↓；←>, < ；←>) and single flip CFin faults (including <↑； > and <↓； >). Conclusion 1 is proved.

Conclusion 2: March-CW (i.e., M0+M1) can detect all SAF, TF, AF, SOF, CFid, CFst faults, and all CFin faults except < ； >.

Proof: Since M1 contains the marching sequence , M1 can detect all SOF faults.

Since M1 includes a marching sequence ), a test vector word with a 0-1 interval is used, so it can detect coupling faults in the words <↑；1/0>, <↓；0/1>, <0；0/1>, <1；1/0> caused by the inversion of all odd bits to the even bits, as well as the above faults caused by the inversion of all even bits to the odd bits. The intervals between the test vector words 0-1 used in other marching sequences of M1 increase by powers of 2, so it can detect coupling faults in the words <↑；1/0>, <↓；0/1>, <0；0/1>, <1；1/0> caused by the inversion of all odd bits to the odd bits, as well as the above faults caused by the inversion of all even bits to the even bits. Therefore, M1 can detect coupling faults in the words <↑；1/0>, <↓；0/1>, <0；0/1>, <1；1/0>.

Combined with Conclusion 1, Conclusion 2 is proved.

Conclusion 3: M0+M1+M2 can detect all SAF, TF, AF, SOF, and CF faults.

Proof: The test vector word used by the M2 marching sequence traverses the possible faults caused by each bit in the word , so M2 can detect all coupled faults in the word.

Combined with Conclusion 2, Conclusion 3 is proved.

3 Analysis and Application

3.1 Analysis of computational complexity

The amount of computation is an important indicator for real-time memory detection, as shown in Table 4.

It can be seen from Table 4 that, under the premise of having the same fault detection capability, the detection time of M0+M1+M2 is much shorter than that of March-17N and Galpat; when u is larger, the detection time of M0, M0′, March-CW, and M0+M1+M2 will be greatly shortened.

3.2 Example Application

For 1 MB RAM, one word consists of 32 bits, so u=32, v=5, 50 MHz bus read and write rate, DSP processing speed is calculated as 500 MHz. The above detection algorithm is used to verify and detect the real-time function of DSP peripheral memory, and the results are shown in Table 5.

It can be seen that M0+M1+M2 can complete the detection of 1 MB memory within 2 s, and the faults cover all SAF, SOF, TF, AF, CFin, CFst, and CFid. Although the detection time of M0+M1+M2 is longer than that of M0, M0′, and March-CW, it can detect more types of faults; M0+M1+M2 can detect all detectable faults, and the detection time is reduced from 15 s to 1.6 s.

This paper considers all static non-link faults of the memory and proposes a progressive test scheme that can detect all SAF, TF, AF, SOF, and CF to complete DSP peripheral memory testing efficiently and quickly.

Compared with March-CW, , and March-17N, the results show that the proposed method can detect the faults missed by March-CW, and the computational complexity of the proposed method is (11N+5v)/u+2N (where each word is u bits, u=2v), which is much faster than 's 11N and March-17N's 17N/u+10N. This method is used in the functional verification of DSP peripheral memory, and the detection of megabyte memory is completed within a few seconds, so that the resource verification of DSP peripheral memory can be completed in real time. In addition, this method can also be extended to the peripheral memory test of other embedded processors.