Application design technology of video compression system based on ADV212 chip

In the past decade, high-definition digital television (HDTV) services have been widely promoted and applied around the world (the United States took the lead in opening the HDTV roadbed cable network in 2003, and China has also determined the plan that HDTV will gradually replace the traditional TV network in a few years). However, due to the huge amount of video data, it is not convenient to store and transmit, and the traditional compression system has the characteristics of low compression quality and weak real-time performance. Therefore, it is of great significance to study the compression system based on high-definition video signals. The new codec chip ADV 212 launched by the American AD company adopts wavelet transform and adaptive arithmetic coding technology, and has the characteristics of hierarchical transmission, focal area compression, multi-scale, multi-resolution analysis and time domain localization, so that the compressed signal can be easily transmitted to the central control console through wired or even narrowband wireless channels, and has the advantages of large compression adjustable range and high compression quality. Based on this, this paper designs an efficient video compression system combining ADV212 with FPGA and DSP.

2 ADV212 structure and function

2.1 Internal structure

ADV212 is a low-cost, single-chip, low-power, all-digital CMOS VLSI. It can generate code streams suitable for most applications while achieving the high-intensity calculations required for JPEG2000 image compression. The chip has a core operating voltage of 1.5V and an I/O voltage of 2.5V to 3.3V. It mainly includes a dedicated wavelet transform engine, 3 entropy encoders, an on-chip memory, and a built-in reduced instruction set (RISC) processor. Image or video data is input by the AD internal 12-bit pixel interface, and the sampling results are input into the wavelet transform engine in interlaced rows. Then, a 5/3 or 9/7 filter is used to decompose each block or frame into sub-bands, and the obtained wavelet coefficients are written into the internal memory. The entropy codec encodes the data to the JPEG2000 standard. The internal DMA engine provides high-bandwidth transmission between memories and high-performance transmission between modules and memories. Figure 1 is the internal functional diagram of ADV212.

Figure 1 Internal functional structure of ADV212

2.2 Analysis of ADV212 functional modules

(1) Wavelet transform engine.

DV212 provides a high-precision wavelet transform processor that can achieve 6-level wavelet decomposition. In encoding mode, the wavelet processor transforms and quantizes the original sampled data and stores the wavelet coefficients in the internal memory.

In decoding mode, the wavelet transform coefficients are read from the internal memory and the original data before encoding is obtained through decoding calculation.

(2) Entropy encoder.

The entropy codec is used to perform background modeling and arithmetic coding on the coding blocks of wavelet coefficients, and can also calculate the distortion required for the best rate and distortion performance during the compression process. Since the entropy coding process has the highest computational requirements in the JPEG2000 compression project, three dedicated hardware entropy codecs are provided within the ADV202.

(3)Internal memory.

The main function of the storage system is to manage wavelet coefficient data and temporary code block feature data, as well as to create, decompose, and store temporary workspaces for JPEG2000 code streams. In addition, the storage system is also used for program and data storage of the RISC processor.

(4)Embedded RISC processor.

ADV212 has a built-in 32-bit RISC processor that can be used to configure, control and manage other dedicated hardware modules and decompose and generate JPEG2000 video streams. The RISC processor has ROM and RAM corresponding to each program and data memory, interrupt controller, standard bus interface and timer counter.

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2.3 Main features

Features a single-chip JPEG2000 compression and decompression solution for video and still images.

The pins are consistent with those of chip ADV202 and support all functions of ADV 202.

Newly added support for JTAG/boundary scan function, power consumption is 30% lower than ADV 202.

The unique spatial super-efficient regressive filtering (SURF) technology can achieve low-power and low-cost beamlet compression, and support up to 6 levels of 9/7 and 5/3 wavelet transforms.

Using 5/3 wavelet the programmable tile/image size can be up to 2048 pixels wide in 3-component 4:2:2 interlaced scan and up to 4096 pixels in single compression mode, with a maximum tile/image height of 4096 pixels.

Supports multiple video interface protocols such as ITU-RB.T656, SMPTE 125M PAL/NTSC, SMPTE 274M, SMPTE 293M (525p), ITU-RB T.1358 (625p), and any video format with a maximum input speed of 65Msps in irreversible mode and 40Msps in reversible mode.

Two or more ADV212s can combine full frame SMPTE274M HDTV (1080i) or SMPTE 296M (720p).

Ability to temporarily interlace SD video source frames to improve quality.

The flexible asynchronous SRAM type master interface enables seamless connection to 16/32-bit microcontrollers and ASICs.

2.4 ADV 212 software configuration

The working mode of ADV212 is set by writing the status word of the register in the initialization firmware. The suffix of the firmware program is *.sea. It is downloaded to the indirect memory of ADV212 through the USB interface. Its address segment is 0x00050000~0x0005EFF, and the data width is 32bits. The ADV212 program coding process using C language is shown in Figure 2.

3 Design of HD Video Compression System Based on ADV212 Chip

This system is based on ADV212 and equipped with a general-purpose processor, which can realize high-definition video signal compression with a resolution of up to 1080 i.

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3.1 Multi-chip encoding mode

Since the maximum data input rate of ADV212 in irreversible and reversible modes is 65Mbps and 40Mbps respectively, and the effective video conversion input data rate is about 124Mbps, at least two ADV212s are required to achieve the encoding and decoding of full-resolution 1080i video signals. During the encoding process, Y data and CbCr data are input to ADV212 through different buses, among which AD212_1 processes the brightness data of 1080i video signals, and ADV202_2 is used to process the chrominance data of 1080i video signals. In order to synchronize the corresponding output data in this application mode, its input data must be in EAV/SAV encoding format. If you want to obtain higher performance, such as lossless compression of 1080i video, you can choose 3 or more ADV212s to process the signal. Figure 3 is a connection diagram of two ADV212 encoding hardware.

In the multi-chip mode of ADV212, the chip is usually used as a slave device during encoding, and can be divided into master/slave or slave/slave mode during decoding. In the master-slave mode, the HVF output of the master chip and the HVF input of the slave chip are connected together, and the SCOMM of the master chip and the slave chip are also connected to the same IO pin of the controller. In the slave-slave mode, the HVF of ADC212 is generated by the same external synchronization signal and the SCOMM is connected to the same IO pin of the controller. In the multi-chip mode, the SW IRQ1 of all ADV212 cannot be masked, and SW IRQ 1 is in the E IRQ IE (external interrupt enable) register.

3.2 System Design

Based on the multi-chip connection mode and efficient compression performance of the ADV212 chip, and combined with the programmability of FPGA + DSP, we designed a video compression system as shown in Figure 4. As can be seen from the figure, the system is mainly composed of four parts: A/D converter, FPGA module, DSP module, and ADV212 encoder/decoder. The functions and technical approaches of each part are as follows:

The A/D conversion is done by ADV7402, which can automatically detect and convert standard analog baseband TV signals into 4:2:2 component digital video data that complies with CC IR656. The D/A conversion during decompression is done by ADV7321.

Figure 4 System structure block diagram.

The FPGA module is the center of the entire system and bridges the signals of each chip in the system. First, the image data is processed (such as denoising) as required, and then the data is divided into two sub-blocks of the same size so that they can be processed in two ADV 212s respectively.

At the same time, it is necessary to provide reset, chip selection, line field synchronization, read and write, and clock signals to ADV212 to control the working sequence and working mode of multiple ADV212 chips, and provide reset signals to DSP. During the working process, FPGA must continuously send feedback information of the working status to the outside. After receiving the "transmission" instruction from the outside, the code stream will be taken out from the memory, and FPGA will convert it into a bit stream format and send it to the channel.

The DSP module is the master controller of the system, which completes the initialization of ADV212 and ADV7402. The JPEG2000 format code stream generated by ADV212 encoding is first sent to DSP for encryption, and then stored in SDRAM to wait for receiving the "transmit" instruction. After receiving the "transmit" instruction, DSP sends the code stream to be sent stored in SDRAM to the parallel/serial conversion DPRAM, and finally converts it into a serial bit stream in FPGA and sends it out.

After the system starts working, the external analog video signal is transmitted to ADV7402. After sampling and quantization, ADV7402 outputs digital video data that meets the requirements. The video data stream is sent to ADV212 for compression encoding through the FPGA bridge. In order to improve the compression rate, the data can be discarded when the video data stream flows through the FPGA to artificially reduce the source data rate that needs to be compressed and encoded.

The compressed data is then transmitted by ADV212 to the interface controller in the FPGA, and the controller outputs the compressed data stream according to the specified interface protocol.

4 Conclusion

Combining the high flexibility of FPGA and DSP, and utilizing the multi-chip mode and efficient compression of ADV 212, a compression/decompression system was designed, which effectively solved the problem of high compression and high quality preservation of high-definition video signals, and laid a good foundation for the launch and popularization of high-definition digital TV services.