Design and implementation of accident scene processing platform based on SOPC technology

Abstract: This paper introduces the design of an accident scene processing platform using the SOPC design method and Altera's Nios soft-core processor as the core. The specific implementation of the two most important parts, the SCCB bus control module and the SRAM read-write control module, is introduced in detail, and the actual simulation results of the SRAM write controller are given. Finally, the design method of SOPC is summarized. Keywords: SOPC; accident scene processing platform; IP core; SCCB bus Introduction The current widespread application of mobile policing enables traffic police to handle the driver and vehicle at the scene of the accident. However, most applications only stay on the transmission of very simple text data such as license plate numbers. If the content of mobile policing can be expanded to image data, and the images and other information of the accident scene can be transmitted to the control center in real time, the accident can be handled more quickly and accurately. SOPC (Systems-on-a-Programmable Chip) is a PLD-based SoC design method strongly advocated by Altera. It has the characteristics of flexible and convenient design. It not only has advantages in product performance, speed and connection, but also can shorten time to market and reduce costs. The accident scene processing platform introduced in this article, which uses the SOPC method and is based on Altera's Nios soft-core processor, is a portable mobile processing system that can realize the functions of on-site data acquisition, wireless transmission, and wireless data exchange with the control center. Accident scene processing platform composition and hardware design platform composition The accident scene processing platform can be divided into five parts: image acquisition part, compression storage part, wireless transmission part, information display part and remote server part, as shown in Figure 1. In addition to the necessary external cameras, input and output devices, wireless modules and large-capacity storage, all control logics are integrated with the processor inside the FPGA, which significantly reduces the size, power consumption and cost of the system. In addition, the impact on design performance caused by unreasonable routing on the PCB board is minimized.

Hardware Design
The hardware block diagram of this design is shown in Figure 2. The input and output devices are controlled using standard GPIO. The GPIO control module has been integrated in Altera's Quartus II software and can be added through the graphical interface of the SOPC Builder software. The wireless module is controlled using a standard serial port, and its control module has also been integrated.
The module that needs to be developed by yourself is the SRAM read-write control module. Because the caching and processing of image data requires a large amount of storage space, and the storage resources provided by the development board are obviously not enough, an external SRAM is also added to the acquisition board, and a read-write control module needs to be developed for them. Design and simulation

of SCCB bus control module and SRAM read-write control module In the design process of this system, the most important and difficult part is to integrate the user IP core you need into the FPGA resources. The following is a detailed introduction to the design and composition of these two modules:

SCCB bus control module
The camera model used in the system is OmniVision's OV7649 CAMERACHIPS chip and its matching CMOS lens. This is a low-voltage CMOS image sensor chip. Through the control of its unique SCCB (Serial Camera Control Bus) bus, it can achieve various forms of image output such as full frame, half frame, sub-sampling, etc. The output format can be selected to be configured as YUV, RGB or original RGB, etc. In addition, automatic exposure control and image gain control can be performed. All configurations are changed through the SCCB bus.
The state machine model can be simplified into 6 states: Idle idle; Bit_Start bit start; Bit_Mid_LOW bit transmission low bit transmission; Bit_Mid_HIGH bit transmission high bit transmission; Bit_End bit transmission end; Trans_End the entire transmission ends. According to the specific jump process, it can be easily completed using the conditional statement in the VHDL language, which will not be repeated here.
TYPE states IS(Idle, Bit_Start,Bit_Mid_LOW,Bit_ Mid_HIGH,Bit_End, Trans_End);
SIGNAL nowState: states;
The following describes the process of filling frame data:
case nowState is
when Idle =>
......
when Bit_Start =>
......
end case;
During the simulation process, since it is necessary to analyze the signal for a long time, it is not possible to list all the simulation results here due to space limitations. In actual engineering use, the SCCB bus control module has been verified to be correct, and it can correctly implement the configuration of the camera, and the quality of the pictures taken has reached the expected level.

SRAM read-write control module
The memory chip selected in the system is IDT71V424. Like all memory chips, the IDT71V424 chip is controlled by three control lines: chip select (CS), read enable (OE), and write enable (WE). The difficulty of the design is not how to write data into SRAM, but how to write data into SRAM according to the data output rate of the camera. The data output of the camera is synchronized by the field synchronization signal (VSYNC) and the line synchronization signal (HREF).
When implemented, the CPU is not directly used to control the CS, WE, and OE signals, but a doWrite signal is generated. When this signal is high, the corresponding CS, WE, and OE signals are controlled to perform write operations, which are implemented in two independent processes. The advantage of this is that the coupling of each part is as small as possible, which is convenient for debugging each part.
In order to synchronize the output data with the write data, the system does not respond to the first field synchronization signal, but counts several field synchronization signals (VSYNC) and waits until everything is running stably before starting to receive data.
The simulation results are shown in Figure 3. In each row cycle, the data is correctly written to the data line. The Data_cam signal is the output data of the camera, which is simulated by even-incremented data as input. Data_sram is the data line of the SRAM. As long as the data of Data_cam is read at the rising edge of each pixel clock pclk, the data can be correctly written.
It can be clearly seen from the simulation results that the design is reasonable and effective. Moreover, in engineering practice, the SRAM controller has also been proven to work reliably.

Design Summary
At present, the number of transistors that a single chip can provide has exceeded the needs of most electronic systems. How to efficiently and fully utilize these device resources has become a major challenge. Almost any electronic system design will use some existing IP modules, such as microprocessors, DSPs, memories, etc. Unlike traditional IC design, the design of embedded software has also been integrated into the design process of SOPC. In the design practice of SOPC, we realize that the revolution of design methods requires a transformation from the traditional process based on functional design to a new process based on functional integration. Integration is also an innovation. In the design process of the accident scene platform, I have the following experience:

Make full use of the flexibility of SOPC design method
Since it is a portable device, volume, power consumption, integration, etc. become the first considerations, and the device selection should serve this goal as much as possible. The essence of SOPC design method is to integrate all modules into a chip to avoid excessive peripheral circuits and devices causing an increase in volume, power consumption and a decrease in reliability. The reason for using USB modules or CMOS lenses to complete image data acquisition tasks is that the control logic and protocol implementation can be solved inside the FPGA, while if analog devices are used, it is inevitable to add peripheral circuits, causing various difficulties.

Systematic and modular design methods and ideas
Systematic and top-down design concepts have been implemented in the design, always focusing on forming a complete closed-loop system through the effective connection and operation of each module. The various modules are organically connected through the Nios soft-core processor. No matter how the specific implementation details of each module are changed, the functions and performance of the original system design will not be changed, and the integrity and feasibility of the system can be guaranteed.
The system is composed of modules, and the biggest advantage of Nios is the modular hardware structure, as well as the flexibility and scalability brought about by it. In the design process based on the team, modularization facilitates the decomposition of the system's tasks, so that everyone can purposefully solve the design and debugging problems of a single module, continuously improve it, and finally integrate the modules organically according to the pre-defined standard interface. This is in line with the current actual development process in the industry and also facilitates the cultivation of laboratory research learning.

System Scalability
Since SOPC Builder in QuartusII software is very convenient for expanding peripheral interfaces and also supports direct updating and upgrading of modules, it makes it easier to expand and improve the system.
Scalability is not only reflected in the upgrade of existing designs. If different parts of the system are modified to different degrees and then recombined, new applications can be brought about. For example, if the wireless module is replaced with a network interface, it can be used as a monitoring system; for example, if the front-end camera part is replaced with the input of special data, it can be used as a remote wireless meter reading system. Such scalability in application also reflects the flexibility and scalability of the design at the beginning, which greatly broadens the application field of the product and also extends the life cycle of the product.