Programmable ASIC Design (Sichuan University)

The "Programmable ASIC Design" course is a practical course focusing on the development of field programmable gate array (FPGA) device design methods. With the development of integrated circuits, programmable ASIC design has become a necessary means for experimental and practical courses on digital circuit systems and digital signal processing. The course study focuses on the development of the popular DE series motherboards at home and abroad. It teaches the internal resource structure of FPGA, carries out the study of Verilog HDL language, and uses EDA software such as QuartusII to carry out case study of digital logic circuits, signal processing and SOPC system design.

    The course focuses on the combination of circuit design practice and theory. Taking examples as the learning center, it will teach you step by step the hardware description language and FPGA design and development techniques, SOPC digital system and hardware acceleration development methods, and enhance the ability of innovative design and practical application.

• Chapter 1：Integrated circuits and programmable ASICs (10 minutes and 25 seconds)

• Chapter 2：Meet programmable ASICs (9 minutes and 40 seconds)

• Chapter 3：FPGA resources (9 minutes and 45 seconds)

• Chapter 4：FPGA on DE2 development board (10 minutes and 54 seconds)

• Chapter 5：DE2 development board resources (11 minutes and 40 seconds)

• Chapter 6：EDA design tools (1) (14 minutes and 37 seconds)

• Chapter 7：EDA design tools (2) (11 minutes and 47 seconds)

• Chapter 8：FPGA setup and download (16 minutes and 35 seconds)

• Chapter 9：VerilogHDL syntax (1) (11 minutes and 57 seconds)

• Chapter 10：VerilogHDL syntax (2) (10 minutes and 29 seconds)

• Chapter 11：verilog HDL modeling example (11 minutes and 31 seconds)

• Chapter 12：FPGA simulation method (8 minutes and 25 seconds)

• Chapter 13：FPGA download verification (7 minutes and 32 seconds)

• Chapter 14：Logic Analyzer Design (12 minutes and 18 seconds)

• Chapter 15：Logic Analyzer Advanced Settings (12 minutes and 30 seconds)

• Chapter 16：Experimental part (35 minutes and 13 seconds)

• Chapter 17：Timing analysis basics (14 minutes and 6 seconds)

• Chapter 18：Timing analysis experiment (15 minutes and 30 seconds)

• Chapter 19：Design of Finite State Machine 1 (13 minutes and 38 seconds)

• Chapter 20：Design of Finite State Machine 2 (9 minutes and 26 seconds)

• Chapter 21：State machine experiment (8 minutes and 37 seconds)

• Chapter 22：Experimental results (21 seconds)

• Chapter 23：DSPBuilder design flow (9 minutes and 38 seconds)

• Chapter 24：How to complete modeling in simulink (17 minutes and 3 seconds)

• Chapter 25：Design model is implemented on FPGA (12 minutes and 16 seconds)

• Chapter 26：FIR filter project (14 minutes and 38 seconds)

• Chapter 27：NiosII soft core processor (10 minutes and 19 seconds)

• Chapter 28：NiosII processor system case (15 minutes and 10 seconds)

• Chapter 29：Introduction to HPS (9 minutes and 53 seconds)

• Chapter 30：HPS design process (9 minutes and 59 seconds)

• Chapter 31：Opencl development process (10 minutes and 3 seconds)

• Chapter 32：Understand the openCL accelerated image processing algorithm process (10 minutes and 49 seconds)