Single-chip CCM PFC and LLC combination controller that meets high performance and power efficiency requirements-EEWORLD

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Computers, servers and flat-panel TVs have always been important targets for energy efficiency regulation agencies. These devices must meet the latest energy efficiency requirements while meeting high performance. As a leading manufacturer, ON Semiconductor has been committed to launching power controllers that meet the latest energy efficiency regulations. This article will introduce the main features and application design points of ON Semiconductor's high-efficiency, high-performance power factor correction (PFC) and half-bridge resonant dual inductor plus single capacitor (LLC) combination controller NCP1910 used in computer ATX power supplies and flat-panel TVs, to help engineers better use NCP1910 for related power supply designs.

Existing solutions and existing problems

The biggest problem with the existing solutions for the above power supply design is the large number of components. First, there must be a PFC controller with main power input undervoltage (LBO) protection, and an LLC controller with input undervoltage (BO) protection and latch function; a comparator for processing the "power good" (PG) signal, and additional circuits for sensing are also essential. In addition, in order to achieve secondary-side overvoltage protection (OVP), a silicon-controlled rectifier (SCR), a comparator and a sensing circuit are required; in order to provide LLC short-circuit protection (SCP) and take into account abnormal PFC working conditions, some other components are required. If all functions can be combined in a single chip, a combined controller can be implemented to solve these problems.

Advantages of high-performance CCM PFC and LLC combination controller

The NCP1910 introduced by ON Semiconductor combines PFC and LLC controllers in a single chip, integrating all the signal exchange (handshaking) functions required by these two converters, which can not only improve reliability, but also support simpler and higher density designs. The NCP1910 adopts SOIC-24 package and is suitable for high-power ATX, all-in-one, server and flat-panel TV power supplies.

Figure 1 is a typical application circuit diagram using NCP1910, which includes a remote PFC section, an LLC section, and a common circuit to achieve on/off, power good (PG), etc.

Figure 1: Typical application circuit diagram using NCP1910

The PFC stage has the following characteristics:

Fixed frequency continuous conduction mode (CCM) PFC is available in 65kHz, 100kHz, 133kHz and 200kHz options;
Programmable overcurrent threshold provides optimized sense resistor;
Over-power limiting can limit current according to the average input voltage;
PFC abnormal protection, in the event of a PFC abnormality, the device stops working even if the input is a high line voltage;
Undervoltage protection prevents damage in case of wrong connections in the feedback network;
Fast transient response to maintain V _bulk regulation: --Overvoltage protection automatically restores the OVP threshold (105% of regulation level); --Dynamic response enhancer uses its internal 200 µA current source to speed up the regulation loop when V _bulk drops below 95% of its regulation level;
Redundant OVP (OVP2) uses a dedicated pin to latch V _bulk OVP;
Adjustable line input undervoltage with 50 ms blanking time to avoid damage at low input voltage;
V _in² feed-forward optimizes power factor;
_{Power Boost can adjust V bulk} under extreme line transient conditions (e.g. 264 Vac → 90 Vac);
Adjustable frequency retardation improves light load energy efficiency;
Soft start;
The totem pole drive capability is ±1.0 A gate driver.

The LLC segment has the following characteristics:

Wide operating frequency range from 25 kHz to 500 kHz;
The fixed dead time on the board is 300 ns to avoid shot-through;
During soft start or restart, a dedicated pin discharges the SS capacitor to ground, providing a smooth output voltage rise. When LLC is turned off by the CS/FF pin (> 1V) or the BO function, the SS pin discharges C _SS and provides a pure soft start.
High voltage driver gate drive is + 0.5 A -1.0 A;
Dual fault protection levels are located at the CS/FF pin:
--CS/FF > 1 V: LLC converter immediately increases switching frequency by grounding _CSS . This is an auto-recovery protection mode; --CS/FF > 1.5 V: Latched when a fault is severe and causes CS/FF to be above 1.5 V;
Adjustable input undervoltage (BO), FB pin voltage accounts for a portion of V _bulk , no high-voltage sense rail is required, which can save power;
NCP1910B has a skip cycle working function. When the feedback pin voltage is lower than 0.4 V, the LLC driver enters the skip cycle mode, reducing the frequency and improving the light load energy efficiency.

Simple design method

The design process using NCP1910 is very simple and can be completed in three steps, as shown in Figure 2. The first step is to design the PFC section, the second step is to design the LLC section, and the third step is to design the signal exchange section.

The BO and PG levels in the circuit are determined by R1, R2, and R3, and there is no need to sense high voltage. When the BO level is at the V _bulk level (such as 300 V, depending on the design requirements of the power system), the LLC stops working; when the PG level is at the V _bulk level, the device notifies the secondary-side monitoring circuit and generates a power failure (Power Fail) signal; when the PFC frequency reverses the input power level, the PFC starts to reduce the operating frequency. The following are the PFC and/or LLC stages using thermal shutdown and overcurrent, overvoltage, undervoltage, overpower, input undervoltage and other protection features, as well as frequency reversal, cycle skipping and other techniques to improve energy efficiency.

The working sequence of NCP1910 is shown in Figure 3. If PFC is not ready, LLC cannot start; once PFC is ready, a 20 ms delay will begin; after the delay, the PGout pin assumes a low level and LLC can start working. When the AC input is removed and the power is turned off, V _bulk decreases, and when it reaches the PG signal, the PGout pin is released (open circuit); if V _bulk reaches the LLC stop level, LLC stops working; or if V _bulk decreases slowly, such as in a light load state, LLC will stop working 5 ms after the PGout pin is released.

Figure 3: Working sequence of NCP1910

Remote on / off: A dedicated pin receives the on/off signal from the secondary-side monitoring chip controlled by an optocoupler; when the on/off pin is released, both PFC and LLC stop working; when the on/off pin is grounded, PFC starts soft-start → PFCok → 20 ms later, LLC starts soft-start.

Figure 4: Remote on/off

Thermal Shutdown (TSD) : Thermal protection function helps to achieve good power supply design. When the junction temperature exceeds 140℃, this function is activated and the driver becomes low; the device resumes operation when the junction temperature drops to a typical value of 30℃.

Figure 5: Thermal shutdown

Frequency Reverse: It can improve light load efficiency. Set V _{fold
to determine the V}_fold value at which the power starts to reverse . When (V _CTRL – V _CTRL(min) ) is less than V _fold , the frequency starts to reverse. The internal clamp limits the maximum power of the reverse. There is no reverse at startup.

Figure 6: Frequency reversal

Relationship between V _CTRL , power and frequency: When the output power decreases, V _CTRL decreases accordingly; when the reverse set point is reached, the frequency decreases linearly; the 65 kHz version sets the minimum frequency internally to 40 kHz.

Figure 7: V _CTRL vs. power and frequency

PFC stage:

1. Line Input Undervoltage (BO) Protection: The Line Input Undervoltage pin receives part of the average input current, so when a low line voltage is sensed, a 50 ms timer is activated. This blanking time is used to help meet the maintenance requirements. If the line voltage is still at a low level at the end of the 50 ms blanking delay, the input undervoltage protection is triggered, the PFC driver is turned off, and the V _CTRL pin is grounded, allowing the device to use soft start when the fault disappears.

Figure 8: Line input undervoltage protection

2. Fast transient response / overvoltage protection (OVP) : When V _FB > 105% V _PREF , the overvoltage protection is activated and the driver output becomes low; when V _FB is lower than 103.2% V _PREF , the device automatically resumes operation.

Figure 9: PFC - fast transient response/overvoltage protection

3. Redundant OVP ( Latch ) : A dedicated OVP2 pin is used to protect large capacitors; a 20 µs filter built into the circuit is used to provide better noise immunity. When the OVP2 comparator is triggered, both PFC and LLC are turned off. When the PFCok signal is assumed to be low, PGout is released to open the circuit, causing LLC to stop working.

Figure 10: PFC-Redundant OVP

4. PFC abnormal detection: The purpose of PFC abnormal detection is that if PFC does not work properly, then even if a high line voltage appears, both PFC and LLC should stop working. For example, when the PFC driver resistor is damaged at a high line voltage. The method to achieve PFC abnormal detection protection is: if V _CTRL remains at the highest level or below the lowest level, such as the V _CTRL pin is abnormally short-circuited for longer than 1 second (t _PFCabnormal ), the PFCok internal signal drops, and the PGout pin is immediately released to open the circuit, notifying the system that the power supply will be turned off; LLC stops working after 5 ms (t _DEL2 ).

5. Undervoltage Protection (UVP)/ Feedback Loop Abnormal Protection: UVP can prevent startup under feedback fault conditions. When V _FB < 8% V _PREF = 0.2 V, UVP is activated and the device is turned off; when V _FB is higher than 12% V _PREF = 0.3 V, the device automatically starts to work.

Figure 11: PFC – Undervoltage protection/Feedback loop abnormality protection

6. Power Boost : The purpose of the PFC Power Boost function is to limit the output power when the input line changes drastically from high line voltage to low line voltage (such as a sharp drop from 264 Vac to 90 Vac at full load) to prevent V _bulk from dropping sharply, which may cause V _out to exceed the regulation range. V _LBO is the average value of V _ac .

_{V LBO} can be pulled down to 2 V (V _LBO(PD) ) when : V _LBO is above 2 V (at high line voltage) and V _CTRL is at maximum for longer than 4 ms (t _PFCflag ); V _bulk is less than 95% of rated output. The PFC Power Boost function is disabled at startup; the maximum pull-down duration is typically 5 ms (t _LBO(PDlimit) ); the switch remains in the open state for a minimum of 70 ms (t _LBO(PDblank) ).

LLC segment: The LLC topology is a half-bridge dual inductor (LL) plus a single capacitor with a constant duty cycle of 50%. The frequency change can be used to improve the voltage regulation effect.

1. One pin for F _max , F _min and F _SS : R _min determines LLC minimum frequency; R _min // R _max determines LLC maximum frequency; R _min // R _SS determines LLC startup frequency; R _SS and C _SS determine soft start duration. Rt pin controls LLC

Figure 12: LLC Control

2. Complete soft-start: The SS pin is grounded when: startup, or CS/FF is higher than V _CS1 (1 V), or BO is activated, or t _DEL2 is over. Only when V _SS is lower than V _SS(RST) , the switch on the SS pin is released and a complete soft-start from startup (restart) is performed.

Figure 13: Complete soft start

3. Skip mode ( only available in B version ) : Skip mode can reduce LLC output pulses under light load, thus avoiding any frequency runaway and improving standby energy consumption.

Figure 14: Skip cycle mode

To help with design, ON Semiconductor also provides a demonstration circuit board (prototype board) with an input voltage of 90V-265V AC and an output of 12V/25A and 5V/2A (for standby).

Figure 15: Demonstration board

The energy efficiency test results show that the energy efficiency level target of the demonstration board, such as typical load energy efficiency and power factor, no-load and standby input energy consumption, are shown in Table 1.

Table 1: Energy efficiency level targets

Summarize

ON Semiconductor's new ATX power supply product NCP1910 high-performance combination controller integrates power factor correction (PFC) and main power segment controller in a single IC. It has PFC independent OVP, PFC dynamic response increaser, PFC light load frequency reversal, wide frequency range LLC, high-voltage driver and excellent OCP, remote on/off control and combination management, which can provide high-efficiency and high-performance power supply design for desktop personal computers and flat-panel TVs.

Keywords：PLL Reference address：Single-chip CCM PFC and LLC combination controller that meets high performance and power efficiency requirements

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