Design of RFID board-level tag based on FPGA technology

Radio Frequency Identification (RFID) technology is an emerging non-contact automatic identification technology with broad application prospects in many fields such as industrial automation, commercial automation, transportation control and management, anti-counterfeiting and military. It uses wireless radio frequency to carry out non-contact two-way data communication to achieve the purpose of target identification and data exchange, and can be used to track and manage almost all physical objects. RFID electronic tags have become the main direction of global automatic identification technology development in the 21st century. At present, RFID has been widely used, and there are several international standards such as ISO10536, ISO14443, ISO15693, ISO18000, EPCGlobal, etc. Among them, ISO18000-6C belongs to the ultra-high frequency radio frequency identification technology standard, which integrates the EPCC1G2 standard. The characteristics of this standard are fast speed, a large number of tags that can be read at the same time, and theoretically more than 1,000 tags can be read; strong functions, with multiple write protection methods; strong security.

In my country, due to the late start of RFID technology, its application areas are not very wide, and its main applications are based on medium and low frequencies, including vehicle management, access control management, etc. At present, UHF RFID technology and its applications are in the early stages of development in my country, and there is no mature UHF electronic tag chip design technology in China.

Here, we first introduce the working principle of electronic tags and the ISO18000-6C standard, and design the overall circuit to implement the ultra-high frequency electronic tag verification platform according to the ISO18000-6C standard. We focus on the design and implementation of the digital baseband part based on EP1C6Q240FPGA. Finally, we give the test results of the platform to verify the correctness and reliability of the platform design.

1 Working principle of electronic tags

The RFID system is usually composed of a reader and a radio frequency tag. The radio frequency tag attached to the object to be identified contains electronic data in a specified format as identification information of the object to be identified. The reader can read the electronic data stored in the tag or write information into the tag without contact, thereby realizing automatic identification and management of various objects. The reader and the radio frequency tag communicate with each other using advanced radio frequency technology according to the agreed communication protocol. The basic communication process is as follows.

(1) Tags within the reader's range receive the carrier energy sent by the reader and power on and reset; (2) Tags receive commands sent by the reader and perform operations; (3) The reader sends selection and inventory commands to identify the tags, selects a single tag for communication, and the remaining tags are temporarily in a dormant state; (4) The identified tag executes the access command sent by the reader, sends data information to the reader through backscatter modulation, enters a dormant state, and no longer responds to the reader; (5) The reader continues to search for the remaining tags, repeating (3) and (4) to wake up a single tag for reading. Until all tags are identified.

The tag transmits data to the reader through backscatter modulation technology. For passive electronic tags, they do not have enough transmission energy, so the reflection strength of the antenna is controlled by changing the matching impedance of the antenna. When the impedance is not matched, the antenna reflectivity is large, and when the impedance is matched, the antenna reflectivity is small, which indicates the presence or absence of output signal.

2 ISO18000-6C Standard

ISO18000-6C standard is:

The working frequency tag should be able to receive the power emitted from the reader in the frequency range of 860 to 960 MHz and be able to communicate with the reader.

Modulation The reader should communicate using DSB-ASK, SSB-ASK or PR-ASK modulation. The tag should be able to demodulate the above 3 types of modulation. The tag backscatter should use ASK or PSK modulation. The tag vendor chooses the modulation form. The reader can demodulate the above 2 types of modulation.

Data Encoding The link from the reader to the tag should use PIE encoding. The tag encodes the reflected scattered data into the subcarrier FMO baseband or Miller modulation of the data rate. The reader sends a command for encoding selection.

Data rate The data rate from the reader to the tag is selected according to the Tari value, and the data rate can range from 40 to 640 Kb/s. [page]

3 Overall Design and Implementation of RFID Board-Level Tag Verification Platform

The board-level tag mainly consists of two parts: analog radio frequency and digital processing. Figure 1 is the structural block diagram of the board-level electronic tag verification platform.

The analog RF part is implemented with discrete components to complete the reception of RF signals. The signal from the RFID reader is filtered through the antenna and impedance matching network, filtered by a 915MHz surface acoustic wave filter, and then envelope detected. It is then passed through a first-order active low-pass filter composed of an op amp, and then the voltage comparator completes the high and low level judgment. The digital part is implemented by EP1C6Q240FPGA to complete ISO18000-6C protocol processing. EP1C6Q240FPGA receives TTL level from the front end and completes PIE decoding, CRC check, command parsing, state transfer, data storage, FMO encoding and other functions. FMO encoding is achieved by outputting anti-phase scatter modulation and changing the reflected impedance of the antenna.

The design of the digital baseband part is implemented on Altera's EP1C6Q240FPGA. After an in-depth study of the protocol content, the digital part of the tag is implemented using a top-down design method. First, the circuit function is described in detail, and the entire system is divided into modules according to the function; then the RTL code is designed using the Vexilog hardware description language. The digital baseband structure block diagram is shown in Figure 2. It includes a decoding module, a cyclic redundancy check (CRC) check module, a state machine module, a CRC generation module, a memory, an encoding module, and a clock division module. The decoding module receives the command signal demodulated by the analog part, decodes the signal into binary data that can be recognized by the digital part of the tag according to the command format specified in the protocol, and sends it to the CRC check module and the state machine module. The CRC check module performs integrity checks on the received command. If it is confirmed to be a valid command, the state machine module is triggered to control the tag to perform corresponding operations, such as reading and writing memory, anti-collision control, etc. After the processing is completed, the data to be sent is sent to the CRC: the generation module generates the corresponding CRC check code, and then sends the data to be sent and the check code to the encoding module. Finally, the encoding module sends it to the analog part in a specific pulse form for processing, and then sends it to the reader using radio frequency technology.

4 Test Results

QuartusⅡ6.0 is a comprehensive integrated design platform for AlteraFPGA/CPLD. The platform integrates almost all the tools required for the design process, including design input, simulation, logic synthesis, layout and routing, timing analysis, chip download and configuration, power analysis, etc. The VerilogHDL program is compiled, simulated and downloaded in the QuartusⅡ6.O environment. After the overall design, PCB board design and implementation, code design, simulation and download, and system debugging, the board-level tag can communicate with the reader (Cetc7RlidReaderV1.O) that supports the ISO18000-6C standard, quickly and accurately send and receive information, and realize the anti-collision function. Figure 3 shows that the board-level tag can decode the command information from the reader and correctly output the FM0 encoding signal under the control of the state machine. Figure 4 shows that the board-level tag can support the ISO18000-6C standard reader to read correctly (the read EPC code is consistent with the tag), the reading effect is good (73 times/10s), and the reading performance is stable. Tests show that the board-level tag can realize the reading and writing functions in the ISO18000-6C standard, and the tag has stable working performance and reliability and can achieve the expected results.

5 Conclusion

According to ISO18000-6C standard, EP1C6Q240FPGA and analog RF discrete components are used. After overall design, PCB board design and implementation, code design, simulation and download, and system debugging, the software and hardware design and implementation of FPGA-based board-level tags are completed. The system has been tested and can work normally, with excellent read and write performance and anti-collision function. On this basis, its security and reliability can be further improved. The designed tag digital circuit RTL code can be directly applied to the development of tag chips, providing a strong guarantee for the next step of designing electronic tag chips that meet the standard.