Electromagnetic compatibility design at circuit board level for high-speed DSP systems

0 Introduction

Printed circuit boards (PCBs) provide electrical connections between circuit components and devices. They are the most basic components of various electronic devices, and their performance is directly related to the quality of electronic devices. With the development of electronic technology, various electronic products often work together, and the interference between them is becoming more and more serious, so the electromagnetic compatibility problem has become the key to whether an electronic system can work properly. Similarly, with the increasing density of PCBs, the quality of PCB design has a great impact on the interference and anti-interference ability of the circuit. In order to achieve the best performance of electronic circuits, in addition to the selection of components and circuit design, good PCB wiring is also a very important factor in electromagnetic compatibility.

With the widespread application of high-speed DSP technology, the corresponding high-speed DSP PCB design is very important. Since DSP is a rather complex, diverse and multi-system digital and analog hybrid system, the interference from external electromagnetic radiation and crosstalk between internal components, subsystems and transmission channels to DSP and its data information has seriously threatened its working stability, reliability and safety. According to statistics, DSP accidents caused by interference account for about 90% of its total accidents. Therefore, electromagnetic compatibility and anti-interference are crucial to design a stable and reliable DSP system.

1 DSP's electromagnetic interference environment

The basic model of electromagnetic interference consists of three parts: electromagnetic interference source, coupling path and receiver, as shown in Figure 1.

Sources of electromagnetic interference include microprocessors, microcontrollers, electrostatic discharge, instantaneous power actuators, etc. With the application of a large number of high-speed semiconductor devices, the edge jump rate is very fast, and this circuit can generate harmonic interference up to 300 MHz. The coupling path can be divided into space radiated electromagnetic waves and voltage and current conducted by wires. The simplest way for noise to be coupled into a circuit is through the transmission of conductors. For example, there is a wire passing through a noisy environment. This wire receives the noise through induction and transmits it to other parts of the circuit. All electronic circuits can receive the transmitted electromagnetic interference. For example, in digital circuits, critical signals are most susceptible to electromagnetic interference; analog low-level amplifiers, control circuits and power supply adjustment circuits are also susceptible to noise.

2 DSP circuit board wiring and design

Good circuit board wiring is a very important factor in electromagnetic compatibility. A poor circuit board wiring and design will cause many electromagnetic compatibility problems, and even adding filters and other components cannot solve these problems.

Correct circuit wiring and design should meet the following three requirements:

(1) There is interference between the various circuits on the circuit board, but the circuit can still work normally;

(2) The external conducted emission and radiated emission of the circuit board are as low as possible and meet the requirements of relevant standards;

(3) External conducted interference and radiated interference have no effect on the circuit on the circuit board.

2.1 Arrangement of components

(1) The first issue in the arrangement of components is to group the components. The principles for grouping components are: grouping by voltage; grouping by digital circuits and analog circuits; grouping by high-speed and low-speed signals; and grouping by current size. In general, they are grouped by voltage or by digital circuits and analog circuits.

(2) All connectors are placed on one side of the circuit board, and cables are avoided from being drawn from both sides as much as possible.

(3) Avoid placing high-speed signal lines close to connectors.

(4) When arranging components, consider shortening high-speed signal lines as much as possible, such as clock lines, data lines, and address lines.

2.2 Layout of ground and power lines

The ultimate goal of ground line layout is to minimize ground impedance, thereby reducing the ground loop potential from the circuit back to the power supply, that is, reducing the loop area formed by the circuit from the source end to the destination end and the ground layer. Usually, the increase in loop area is caused by the gap in the ground layer. If there is a gap in the ground layer, the return line of the high-speed signal line is forced to bypass the gap, thereby increasing the area of ​​the high-frequency loop, as shown in Figure 2.

In Figure 2, signals are transmitted between the high-speed line and the chip. In Figure 2(a), there is no ground gap. According to the principle that "current always takes the path with the least impedance", the loop area is the smallest. In Figure 2(b), there is a ground gap. The ground loop area increases, which has the following consequences:

(1) The radiation interference to space increases, and it is easily affected by the magnetic field in space;

(2) The possibility of magnetic field coupling with other circuits on the board increases;

(3) Due to the increase in loop inductance, the signal output through the high-speed line is prone to oscillation;

(4) The high-frequency voltage drop on the loop inductance constitutes a common-mode radiation source and generates common-mode radiation through external cables.

Usually, the gaps in the ground are not added consciously when dividing the ground. Sometimes the gaps are caused by the vias on the board being too close. Therefore, this situation should be avoided as much as possible in PCB design.

The layout of the power line should be considered in combination with the ground line to form a power supply line with the smallest characteristic impedance possible. In order to reduce the characteristic impedance of the power supply line, the power line and the ground line should be as thick as possible and close to each other to minimize the area of ​​the power supply loop, and different power supply loops should not overlap each other. A high-frequency decoupling capacitor with a capacity of 0.01 to 0.1 μF should be added between the power pin and the ground pin of the integrated chip. In order to further improve the low-frequency characteristics of the power supply decoupling filter, a high-frequency decoupling capacitor and a 1 to 10 μF low-frequency filter capacitor should be added to the power supply input end.

In a multi-layer circuit board, the power layer and the ground layer should be placed in adjacent layers, thereby generating a large PCB capacitor on the entire circuit board to eliminate noise. The fastest critical signals and integrated chips should be placed on the side close to the ground layer, and non-critical signals should be placed on the side close to the power layer. Because the ground layer itself is used to absorb and eliminate noise, it is almost noise-free.

2.3 Arrangement of signal lines

Incompatible signal lines can generate coupling interference, so they should be isolated in the layout of signal lines. The following measures should be taken during isolation:

(1) Incompatible signal lines should be kept away from each other and not parallel. Signal lines distributed on different layers should be perpendicular to each other, so as to reduce the coupling interference of electric and magnetic fields between lines;

(2) High-speed signal lines, especially clock lines, should be as short as possible. If necessary, isolated ground lines can be added on both sides of high-speed signal lines;

(3) The layout of signal lines is best arranged according to the order of signal flow. The input signal line of a circuit should not be folded back to the input signal line area, because the input line and the output line are usually incompatible.

When the transmission delay time Td>Tr (Tr is the pulse rise time of the signal) of the high-speed digital signal, the impedance matching problem should be considered. Because incorrect terminal impedance matching will cause signal feedback and damped oscillation. There are four common methods for line terminal impedance matching: series source termination method, parallel termination method, RC termination method, and Thevenin termination method.

(1) Series source termination method

Figure 3 shows the series source termination circuit.

Between the source impedance Zs and the impedance Zo distributed on the transmission line, a source termination resistor Rs is added to complete the impedance matching. Rs can also absorb the feedback of the load. Here, Rs must be as close to the source as possible. In theory, it should be a real value in Rs=Zo-Zs. Generally, Rs is 15~75Ω.

(2) Parallel termination method

Figure 4 shows a parallel termination circuit. Add a parallel termination resistor Rp, so that Rp matches Zo after being connected in parallel with ZL. This method requires a source drive circuit to drive a higher current, which consumes a lot of energy, so it is not applicable in systems with low power consumption.

(3) RC termination method

Figure 5 shows the RC termination circuit. This method is similar to the parallel termination circuit, but capacitor C1 is introduced. In this case, R is used to provide impedance matching Zo. C1 provides drive current for R and filters out RF energy from the transmission line to ground. Therefore, the RC termination circuit requires less source drive current than the parallel termination method. The values ​​of R and C1 are determined by Zo, Tpd (loop transmission delay) and the terminal load capacitance value Cd. Time is a constant, RC=3Tpd, where R∥ZL=Zo, C=C1∥Cd.

(4) Thevenin termination method

Figure 6 shows the Thevenin termination circuit. The circuit consists of a pull-up resistor R1 and a pull-down resistor R2, so that the logic high and logic low match the target load. The values ​​of R1 and R2 are determined by R1∥R2=Zo, and the value of R1+R2+ZL must ensure that the maximum current does not exceed the drive circuit capacity.

3 Conclusion

This paper analyzes the electromagnetic environment of electronic products, identifies the main causes of interference in high-speed DSP systems, and analyzes the multilayer board layout, device layout, and PCB wiring of high-speed DSP systems to provide effective measures to reduce interference and improve electromagnetic compatibility of DSP systems. The effectiveness and reliability of high-speed DSP systems are guaranteed from the design level. Reasonable layout design, noise reduction, interference reduction, and avoidance of unnecessary mistakes play an inestimable role in the performance of the system.