Design of Hardware Driving Circuit for CCD Based on FPGA Chip

The realization of CCD driving circuit is a key issue in CCD application technology. In the past, most of the driving circuits were realized by ordinary digital chips, and the CCD peripheral circuits were complicated. In order to overcome the shortcomings of the above methods, VHDL hardware description language and FPGA technology were used to complete the realization of the driving timing circuit. This method has a short development cycle, and the driving signal is stable and reliable. After the system function module is completed, it can be simulated by computer first, and then put into actual use, which reduces the risk of use.

1 Hardware Design

The core device of the CCD hardware drive circuit system is the SPARTAN series chip XC3S50; the CCD uses the CCDTH7888A image sensor of Atmel; the CCD drive pulse is provided by XC3S50, and after the pulse signal is generated, the drive module transforms the pulse voltage to make it meet the drive voltage requirements of TH7888A. The CCD pixel output voltage is processed by the A/D conversion module processing circuit VSP2272 chip to obtain a digital signal. Finally, in order to facilitate transmission and facilitate the subsequent module to process the digital signal, the digital signal is converted from TTL level to LVDS level for output. The whole system is shown in Figure 1.

1.1 TH7888A Introduction

The CCD image sensor is TH7888A produced by THOMSON. It is a high-performance frame transfer area array CCD device that uses a four-phase pulse drive and provides an electronic shutter function; at the same time, it has two output modes: single-channel output and dual-channel output. Its main performance parameters are as follows:

The photosensitive area and storage area are both 1024×1024 pixels; the speed can reach over 30 images/s; the pixel size is 14 mm×14 mm; the photosensitive area is 14.34 mm×14.34 mm; the spectral wavelength range is between 400 and 700 nm; and the pixel output frequency is 20 MHz.

1.2 XC3SC50 Introduction

XC3S50 belongs to the FPGA (field programmable gate array) of the SPARTAN3 series of XILINX. It is a high-performance device with the following features: the device uses 90 μm processing technology; it has the characteristics of high performance and low power consumption; the logic density reaches 1 728 available gates; 3-way power supply, that is, I/O port power supply is 1.2~3.3V, core power supply is 1.2V, auxiliary function power supply is 2.5V; it has 2KB distributed RAM and 7KB BLOCK RAM, and advanced logic clock management function. Ahera's QuartusⅡ development system provides application design support.

2 Software Design

The CCD drive timing is described in VHDL. VHDL is a language that can describe the function of hardware circuits and signal connection relationships. It has the characteristic of representing hardware circuits more effectively than circuit schematics. Due to its advantages such as being independent of hardware circuits, it can greatly improve development efficiency when used to design circuits.

From the structure of the chip, we can know that one cycle of CCD is divided into two stages: photosensitivity and transfer, as shown in Figure 2.

The photosensitive stage, i.e. the rising edge stage of A, mainly realizes three functions: charge accumulation of the photosensitive array, charge transfer from the frame storage area to the transfer register, and charge output from the transfer register to the output amplifier (i.e. row transfer); the transfer stage, i.e. the falling edge stage of A, mainly completes the transfer of the charge accumulated by the photosensitive array to the frame storage area (i.e. frame transfer), and clears the invalid charge in the frame storage area. The specific working process is analyzed as follows:

In the photosensitive stage, i.e., the rising edge stage of A, P1, P2, P3, and P4 remain unchanged, and the photosensitive array and the frame storage area are in a blocking state, and no charge transfer occurs between the two. However, the photosensitive array will accumulate charges when exposed to external light sources. While the charges are accumulating, under the control of the readout register clocks L1 and 2, a row of charges will be read out first. After reading the first row of signals, a row transfer will be performed. Under the control of the register clock, the signal in the register clock M1 will be transferred to the register M2, and then transferred to the registers M3 and M4 again. During the row transfer, the readout register clocks L1 and L2 remain unchanged, and no pixel signal is output. After the row transfer is completed, the second row of charges is read out; each time a row of signals is read out, a row transfer is performed, as shown in Figure 3. After 1056 cycles, the photosensitive stage is completed. The transfer stage is the falling edge stage of the gated clock A, as shown in Figure 4. The frame transfer control signals P1, P2, P3, and P4 are the same as the row transfer control signals M1, M2, M3, and M4, and are always valid. The read register clocks L1 and L2 are invalid and no data is output. After the frame transfer is completed, it enters the photosensitive stage. The storage area first performs a row transfer and starts the signal output. At the same time, the pixels in the photosensitive area enter the charge accumulation. This constitutes a cycle of TH7888A operation.

The main clock pulse period is set to 50 ns, and then the main clock is divided by 4 to generate L and R. L will be used as the basic waveform to generate and control L1, L2 and M-type waveforms in the future. The duty cycle of L is 2:2, and the duty cycle of R is 3:1. A cycle counter CL is built for L, and its range is 0 to 1 065. In the photosensitive stage, that is, the rising edge stage of A, when CL is less than 1057, L1=L. In the rest of the stages, L1 is low level, and L1 is inverted to L2; when 1057

3. Driver Implementation and Simulation Results

Max+PlusⅡ is a development and design platform launched by Altera. It is powerful and can generate text files and waveform files. It supports hierarchical design and top-to-bottom design methods and VHDL language. It can compile and generate various files that can be downloaded to various FPGA devices, and can also perform simulation to verify the feasibility of the design.

Hardware Description Language (VHDL) is a standard language used to describe the structure and function of integrated circuits. Designers do not need to use gate-level schematics, but instead describe the functions according to the design goals, thereby speeding up the design cycle. The design of VHDL components is independent of the process, which facilitates process conversion. Based on the above advantages and the above timing analysis, the system uses VHDL language to implement the CCD drive timing circuit. Since the system's one-time cycle is relatively long, about 200 ms, the END TIME during waveform simulation is relatively large. Figure 5 shows the waveform simulation of the photosensitivity stage, and Figure 6 shows the waveform simulation of the transfer stage.

It can be seen from the figure that the waveform generated by the design is completely consistent with the pulse required for the driving requirements in the technical manual of TH7888A, and can meet the driving requirements of TH7888A.

4 Conclusion

Using XILINX company's series FPGA-SPARTAN chip, the VHDL language input method was used in the QuartusⅡ5.0 development environment to develop and design a high-resolution full-frame CCD TH7888A drive circuit, which can generate drive pulses that meet the requirements of TH7888A. Compared with the commonly used drive methods in the past, its area is greatly reduced. The use of FPGA for design simplifies the circuit system of the CCD drive circuit. After the entire design is programmed, it is simulated and the timing is verified to be correct before downloading it to the device, and then the circuit is tested and verified until the expected effect is achieved. Such a design is more convenient to modify. You only need to modify the program. There is no need to replace the device or modify the design circuit like the traditional design method. Experiments have proved that applying VHDL to the design of CCD drive circuits can meet the system's high speed and circuit integration requirements.