Counter-based random single-input transition test sequence generation

With the development of VLSI and system-on-chip (SoC), IC testing faces more and more difficulties. In particular, the problem that the power consumption in test mode is much higher than that in working mode has attracted the attention of researchers. With the continuous improvement of IC operating frequency, integration and complexity, the power consumption of IC is also growing rapidly. Taking Intel processor as an example, its maximum power consumption increases by about 1 time every 4 years. As the feature size of manufacturing process decreases, the static power consumption of CMOS tube increases sharply and shows an exponential growth trend. This brings a series of practical problems, because excessive power consumption will cause the IC operating temperature to rise, resulting in the drift of the operating parameters of the semiconductor circuit, affecting the normal operation of the IC, reducing the chip yield and reliability, and even causing the circuit to fail [1]. Therefore, low-power testing is becoming more and more important for today's VLSI system design. It has become a trend to consider low-power testing issues in the process of chip testing. Especially in the current deep submicron process, the line width is getting smaller and smaller, so the requirements for the electron density on the line are becoming more and more stringent. As the temperature rises, the electromigration speed becomes faster and faster, resulting in an increase in the failure rate of the connection, thereby reducing the reliability of the entire circuit. The temperature increase caused by high power consumption will also reduce the migration rate of carriers, increase the switching time of transistors, and thus reduce the performance of the system.

1 Mathematical Estimation Model of CMOS Circuit Energy and Power Consumption

The power consumption in CMOS VISL is mainly divided into two categories: static power consumption and dynamic power consumption[2]. Static power consumption is mainly generated by leakage current. Due to the complementary symmetry of CMOS circuit structure, only one tube is turned on at the same time, and the leakage current is very small. Therefore, static power consumption is not the main part of system power consumption. Dynamic power consumption comes from the short-circuit current when the device undergoes a "0/1" or "1/0" transition and the power consumption caused by charging and discharging the load capacitor. Dynamic power consumption is the main source of circuit power consumption[3].

In a CMOS circuit, the average dynamic power consumption Pd of a CMOS logic gate can be expressed as [4]:

According to formula (1), the dynamic power consumption in CMOS VISL mainly depends on three parameters: power supply voltage VDD, clock frequency f, and probability factor ? ο that reflects the node switch flipping activity rate in the circuit. Reducing the power consumption of the circuit by reducing the power supply voltage VDD and clock frequency f is at the expense of reducing the circuit performance. Therefore, it is usually adopted to reduce the circuit switch flipping activity rate ? ο during the test to reduce the power consumption. This method will not reduce the performance of the circuit and is the mainstream technology for reducing power consumption.

2 RSIC test sequence generation

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First, initialize the shift register SR to (0, 0, 0, ..., 0), use the enable signal to set the flip-flop (FF) to "1", and both FF and SR are controlled by the common test clock signal Clock. The test vector generated by SR in the (n+1) clock cycle is: {(0, 0, 0, ..., 0), (1, 0, 0, ..., 0), (1, 1, 0, ..., 0), (1, 1, 1, ..., 0), ... (1, 1, 1, ..., 1)}. When the next clock signal arrives, the "AND" gate makes the first level of SR "0". After n clock pulses, the output of SR is {(0, 1, 1, ..., 1), (0, 0, 1, ..., 1), (0, 0, 0, ..., 1), ..., (0, 0, 0, ..., 0)}, and then continue to repeat the above process over and over again.

After initialization, the output of Counter remains steady within (2n+1) clock cycles, while SR generates (2n+1) different test vectors. Under the action of the signal Counter-Clock, SR and Counter perform "XOR operation on corresponding bits" to generate (2n+1) single input change (SIC) test vectors. It can be used for low-power testing of integrated circuits.

3 Experimental verification

In order to verify that the RSIC test sequence can reduce the power consumption during the test, the power consumption analysis experiment of the above decoder is carried out using Xilinx's dedicated power consumption analysis tool - XPower.

The FPGA used in the experiment is the XC3S400 of the Spartan3 series, which has a TQ144 package, a speed grade of -6, a DC power supply voltage of 3.3 V, and a maximum clock frequency of 50 MHz.

At different clock frequencies, the pseudo-random full test sequence (MSIC) as shown in Figure 2 and the random single input transition (RSIC) test sequence as shown in Figure 3 are applied to the main logic circuit of the CC4028 decoder, and the measured average dynamic power consumption is shown in Table 1.

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From Table 1, we can see that:

(1) As the clock frequency increases, the average dynamic power consumption of the decoder continues to increase, which is consistent with the theoretical analysis formula (1).

(2) Compared with the MSIC test sequence, the RSIC test sequence can reduce the dynamic power consumption during testing at different clock frequencies.

Due to the widespread use of BIST, the research on its low-power design is very active and has become a very important research direction. However, it is not advisable to reduce the power consumption during the test by reducing the power supply voltage VDD and the clock frequency f, because this will affect the performance of the circuit and the efficiency of the test. However, reducing the probability factor of the switch flip activity rate of the circuit will not affect the normal progress of the test. The research in this paper shows that the single-input jump test sequence has a higher correlation than the multi-input jump test sequence. During the test process, it can effectively reduce the switch flip activity rate of the internal nodes of the circuit under test? , so as to achieve the purpose of reducing the test power consumption.

References

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[2] CORNO F, PRINETTO P, REBAUDENGO M, et al. A test pattern generation methodology for low power consumption [J]. IEEE VTS, 1998: 453-457.

[3] VIRAZEL A, WUNDERLICH H J. High defect coverage with low-power test sequences in a BIST environment[J]. IEEE Design & Test of Computers, 2002, 18(6): 44-52.

[4] Gan Xuewen, Mo Bangyun. A review of low-power CMOS logic circuit design[J]. Microelectronics, 2000, 30(8): 263-267.

[5] Wang Yi, Fu Xinghua. Research on low power single input transition test theory. Microelectronics and Computers, 2009, 26(2): 5-7.

[6] IOANNIS V, ANTONIS P.An efficient built-in self test method for robust path delay fault testing[C].Jornal of Electronic testing: Theory and Application 8.1996: 219-222.