Siemens TIA: Application of Memory Indirect Addressing-EEWORLD

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In STL, the following options are available for indirect addressing:

Memory Indirect Addressing

For memory indirect addressing, you store the address in a variable. The variable can be of the WORD or DWORD data type. The variable can be located in the memory area "Data" (DB or DI), "Bit memory" (M) or "Temporary local data" (L). In the S7-1500, FB parameters can also be used to save addresses. If the variable is located in a data block, this must be a general access data block.

The following examples show the application of memory indirect addressing:

Addressing in STL	illustrate
UE [MD 2]	// Perform an AND logic operation on the variable input bits. The address of the input bits is located in memory double word MD2.
=DIX[DBD 2]	// Assign the RLO to the variable data bit. The address of the data bit is located in the data double word DBD2.
L EB [DID 4]	// Load variable input bits into ACCU 1. The input byte address is located in instance double word DID4.
AUF DB [LW 2]	// Open a variable data block. The number of the data block is located in the local data word LW2.

In case of register indirect internal area addressing, the bit address and byte address are only indexed by the address register (such as P#10.0). The storage area to which the address in the address register applies is not entered before the instruction is written. The address in the address register is then moved to the storage area specified in the instruction.

Possible memory areas are "Input" (I), "Output" (Q), "I/O" (PI or PQ), "Bit memory" (M), "Temporary local data" (L) and "Data" (DB or DI). If the operand is located in a data block, this must be a general access data block.

When register indirect internal area addressing is input, an offset is specified after the address register is specified. This offset is added to the contents of the address register without changing the address register. The offset also has the format of a pointer. A pointer must be specified and must be entered as a constant (such as P#0.0 or P#2.0).

The following example shows the application of register indirect internal area addressing:

STL	illustrate
LAR1 P#10.0	// Load the pointer (P#10.0) into address register 1
L IW [AR1, P#2.0]	//Increase the data in address register 1 (P#10.0) by the value in offset P#2.0. //Load the contents of input word IW12 into accumulator 1
L IW [AR1, P#0.0]	//Increase the data in address register 1 (P#10.0) by the value in offset P#0.0. //Add the contents of input word IW10 to accumulator 1

In case of register-indirect cross-area addressing, the address register is used to index the entire address of the operand. That is, the bit address and byte address, as well as the memory area. Possible memory areas are "Input" (I), "Output" (Q), "I/O" (P), "Bit memory" (M), "Temporary local data" (L) and "Data" (DB or DI). If the operand is loaded into a data block, then the data block must be accessed normally, otherwise the operand must have the reservation setting "Set in IDB".

In the instruction, only the operand width is written. Possible operand widths are bit, byte, word and doubleword.

The following example shows the application of register indirect cross-region addressing:


LAR1 P#M10.0	// Load the cross-area pointer (P#M10.0) into address register 1
LW [AR1, P#2.0]	//Increase the data in address register 1 (P#M10.0) by the value in offset P#2.0. //Load the contents of memory word "MW12" into accumulator 1
LAR1 P#A10.0	// Load the cross-area pointer (P#A10.0) into address register 1
LW [AR1, P#2.0]	//Increase the contents of address register 1 (P#A10.0) by the value in offset P#2.0. //Load the contents of output word QW12.0 into accumulator 1

Description
of the special features in the S7-1500
In the S7-1500, special rules apply to data exchange via address registers and data block registers:
Outside the block, the values in the registers no longer exist. The registers are also reset when the language in the block is changed.
If you access operands of the BYTE, WORD or DWORD type via register indirect addressing, the address must start with a byte limit.
Example:
LAR1 P#0.0
L MW [AR1, P#0.0] // P#0.0 + P#0.0 = P#0.0 - Addressing is permitted, because P#0.0 points to the byte limit.
L MW [AR1, P#2.1] // P#0.0 + P#2.1 = P#2.1 - Addressing is not permitted, because P#2.1 does not point to the byte limit.

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