8K smart camera based on graphene heat dissipation

0 Introduction

With the popularity of 4K TV (resolution: 3 840×2 160, about 8 million pixels) and people's pursuit of the ultimate picture quality, 8K TV (resolution: 7 680×4 320, about 33 million pixels) has become a research hotspot. In order to meet the needs of TV, this paper designs an 8K smart camera based on graphene heat dissipation. Compared with 4K cameras, the color saturation and layering of the camera are greatly improved. Due to the small size of the camera and the high heat generation of the chip, the heat dissipation requirements are extremely high. Therefore, this paper uses graphene materials with good heat dissipation effect to dissipate the heat of the product.

The 8K smart camera based on graphene heat dissipation developed in this paper has good image quality, stable performance, good heat dissipation effect, and has excellent application and development prospects. This paper focuses on the main circuit development of the camera hardware and the graphene heat dissipation design scheme.

1 Hardware Design

The smart camera uses Rockchip RK3588 as the main control, Sony IMX435 as the sensor, and graphene for heat dissipation. The sensor IMX435 transmits the collected image information to the main control RK3588 through the MIPI signal. The main control encodes and decodes the received image and sends it to the TV through HDMI2.1. The TV displays real-time image information, thus realizing 8K ultra-high-definition presentation from the camera to the TV. The signal flow diagram of the 8K smart camera is as follows:

1.1 Introduction to RK3588

RV3588 adopts the fourth-generation codec technology, with up to 6 billion internal transistors, 6 TOPs NPU computing power, and an eight-core (4×Cortex-A76 + 4×Cortex-A55) 64-bit big and small core architecture. The main frequency supports 2.4 GHz and 1.8 GHz, and the performance and power consumption are perfectly combined. RK3588 adopts Rockchip's third-generation image vision processing technology, with an internal integrated 8KISP, supporting multi-camera access, wide dynamic contrast enhancement, 3D noise reduction and distortion correction and other technologies. The chip has built-in rich high-speed interfaces such as USB3.1, USB2.0, PCIe3.0, PCIe2.0, TYPE-C, etc., which is easy to expand, and the system supports Android and Linux OS.

1.2 IMX435 Introduction

Sony IMX435 supports up to 8K@60, a cost-effective energy-saving CMOS sensor. The natural conversion gain technology can make the IMX435 have a higher SNR in the dark. The chip also supports 6 native sensitivity settings including ISO50, ISO200, ISO800, ISO12800, ISO102400, ISO1638.4 K.

1.3 Graphene heat dissipation

Graphene is a revolutionary material with excellent thermal conductivity. It has excellent heat dissipation effect when used in chip heat dissipation, greatly improving the stability of the chip. Graphene is currently the carbon material with the highest thermal conductivity, with a thermal conductivity of up to 5,300 W/mK.

1.4 Hardware Design

The hardware circuit of the smart camera mainly includes the main control circuit, sensor circuit, power circuit, clock reset circuit, etc. The hardware circuit is shown in Figure 2:

The whole system is powered by a 5 V/2 A power adapter. The reset and clock circuits can ensure the normal operation of the system. DDR is a random access memory, and Flash is used to store programs. The smart camera collects image information through the sensor Sony IMX435, and transmits the collected image information to the main control RK3588 through the MIPI signal. The main control encodes and decodes the received image information, and then sends the image to the 8K TV through the HDMI2.1 interface, thereby realizing end-to-end 8K presentation. In order to make the main control chip, sensor chip and system stable, this design uses graphene to dissipate heat for the chip, which perfectly solves the problem of chip heat dissipation.

The 24 MHz crystal oscillator of the RV3588 chip and the internal feedback circuit together constitute the clock circuit of the system. The low level of the nPOR pin of the chip is effective and is used to reset the chip. The reset time is greater than 4 μs to ensure stable operation of the chip. The chip has two PLL power supplies, namely PLL_AVDD_0V8 and PLL_AVDD_1V8. The power decoupling capacitor must be placed close to the pins in the design. To prevent interference with the PLL, it must be powered separately. The core voltage of the chip CPU power supply is 0V8, and the power supply capacity of the power chip LDO is greater than 1A5. When laying out the PCB, the capacitor must be close to the chip pins, otherwise the system will be unstable. The core voltage of the chip Logic and NPU power supplies is 0V8, and the power supply capacity of the power chip LDO is greater than 2 A. When laying out the PCB, the capacitor must be close to the chip pins, otherwise the system will be unstable. The voltage value of LPDDR4 is 1.1 V. The power supply of DDR particles must use the same power supply network. The capacitor is placed close to the chip. VCC_DDR generates Vref_CA voltage through a voltage divider resistor. The voltage divider resistor accuracy requires the use of 1% precision resistors.

When designing the PCB, the XIN and XOUT signals of the crystal oscillator are all grounded, and these signals are guaranteed to have a complete reference ground. The power line or high-speed signal cannot pass through the bottom of the crystal circuit, and there are no more than two vias. The crystal oscillator is placed close to the main control. The "3 W" principle must be maintained between different signal lines in the DDR group and between two adjacent signal lines between groups. The line length error of the CLKP and CLKN differential pairs is less than 5 mil, the line length error of DQS, DM and DATA is less than 10 mil, and the line length error of the DQSnP and DQSnM differential pairs is less than 5 mil. FLASH keeps the signal reference plane intact to avoid signal routing through the power segmentation area, and the spacing between adjacent signal routings is maintained at the "3 W" principle.

The sensor MIPI differential signal keeps the GND reference plane intact. The differential pairs are of equal length and less than 5 mil. The PCB traces of the differential pairs control the differential impedance to 100 Ω±10%. The decoupling capacitors of the controller power supply should be placed close to the pins. The spacing between the differential pairs and other signals follows the 3 W principle.

4 Conclusion

This paper designs an 8K smart camera based on graphene heat dissipation, which is directly connected to the TV through the HDMI2.1 interface, giving users a perfect 8K end-to-end high-definition presentation. In order to ensure the stability of the camera performance, this design uses graphene to dissipate heat for the chip.

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