In-depth analysis of key technologies and MCU solutions for automotive zone controllers

After a century of development, the automotive industry has entered its most exciting moment in history, with technological advances expected to bring unparalleled safety, higher productivity and better environmental benefits. But pure electric vehicles with autonomous driving capabilities cannot become mainstream or affordable overnight. OEMs realize that they need to establish the right architectural foundation for current and future cars. The regional controller is an important part of the vehicle EE architecture. This article discusses the key technologies and MCU solutions for implementing the regional controller.

The regional controller is a node in the car. It provides power distribution, data connection, I/O acquisition and drive requirements for various sensors, actuators and other devices in a physical area of ​​the car. The MCU is the brain of the regional controller. The MCU in the regional controller generally needs to have powerful processing capabilities, rich communication interfaces, and a certain level of functional safety and information security. The following introduces some key technologies and MCU solutions for regional controllers.

1. High-performance multi-core processor

EE architecture vehicles centered around regional controllers and central computing units will reduce the number of ECUs in the vehicle, but will also increase the processor load of some ECUs because more functions are deployed to them. Physically, the regional controller is the logical concentration point of multiple ECUs, which places higher demands on the computing power of the MCU in the regional controller. In traditional ECUs with a single function, a low-performance single-core MCU is often sufficient to meet the requirements, while for regional controllers, high-performance multi-core MCUs are often required to meet the requirements. In a multi-core MCU, each core can run a single function, and multiple cores can realize multiple functions, thereby realizing the integration of multiple ECU functions.

The TC3xx microcontroller is the second generation of AURIX™ products, equipped with up to six TriCore™ 1.62 embedded cores, each with a clock frequency of up to 300MHz. The following figure is a block diagram of the TC39x series MCU in the TC3xx family. The computing power of TC39x reaches 4000 DMIPS.

Figure 1: TC39x Block Diagram

The TC4xx microcontroller is the third generation of AURIX™ products, equipped with up to six TriCore™ 1.8 embedded cores, each with a clock frequency of up to 500MHz, and an integrated PPU coprocessor that can achieve fast vector operations, basic neural network algorithms, and other complex mathematical algorithms. The PPU can be used in future regional controllers for modeling, model predictive control, and anti-intrusion detection and other information security algorithms. The figure below is a block diagram of the TC4Dx MCU in the TC4xx family. The computing power of TC4Dx reaches 8000DMIPS+72GFlops*1. 72GFlops is contributed by the PPU.

Figure 2: TC4Dx Block Diagram

*1. FLOPS is the number of floating point operations per second. 1GFLOPS = one billion (=10^9) floating point operations per second. Taking Multi-Layer Perception (MLP) as an example, when the number of input layer neurons = 14, the number of hidden layer neurons = 20, and the number of output layer neurons = 1, about 1.7GFLOPS of computing power is required.

2. Connectivity and interoperability

In the regional controller system, each sensor and actuator is connected to the local regional controller according to its location, and then the regional controller performs some data frame format conversion, aggregates the data and transmits the data to the central processing unit via high-speed Ethernet. The regional controller generally communicates with the sensors and actuators mounted on it through the controller CAN or LIN bus, or communicates with the camera or other ADAS sensors through low-speed Ethernet or LVDS. This requires the main control MCU of the regional controller to have a wealth of CAN and LIN communication interfaces and high-speed Ethernet interfaces. In the process of data forwarding by the regional controller, the problem of communication delay also needs to be considered. In the centralized architecture, most of the control and execution commands are issued by the central processing unit. Some commands (such as chassis and power) have strict requirements for delay, so there are also requirements for the delay time from high-speed Ethernet to CAN/LIN/low-speed Ethernet interface in the regional controller.

TC3xx/TC4xx family products have abundant CAN/LIN/Ethernet communication interfaces.

Figure 3: TC39x/TC4Dx CAN/LIN/Ethernet Channel

The TC4xx product integrates a dedicated hardware communication routing module CRE (CAN Routine Engine)/DRE (Data Routine Engine). One CAN module in the TC4xx integrates four CAN nodes. When the CAN nodes in the same module perform data communication, CAN data forwarding can be directly achieved through CRE without CPU and software intervention. When CAN nodes in different modules perform data forwarding or data forwarding between CAN nodes and Ethernet, data forwarding can be directly achieved through CRE+DRE, also without CPU and software intervention.

Figure 4: TC4xx CRE DRE

This hardware routing engine directly implements data forwarding, which greatly reduces data delay. The forwarding delay from CAN to Ethernet can be as short as 15us, and the forwarding delay from CAN to CAN can be as short as 5us.

Figure 5: TC4xx Communication Latency

In the future central integrated EE architecture, the amount of communication data continues to increase, and high-speed Ethernet gradually becomes the backbone network in the EE architecture. In order to consider data communication security and redundancy, the Ethernet ring network architecture has gradually become the mainstream, and the regional controller and the central control unit are nodes in the Ethernet ring network. TC4Dx has 2 5Gbps high-speed Ethernet interfaces and 4 10/100Mbps interfaces. The 2 high-speed Ethernet interfaces are connected to the Ethernet ring network (1 in and 1 out), and the 4 low-speed Ethernet interfaces can be connected to radar or camera sensors. The 2 high-speed Ethernet interfaces can directly forward Ethernet frames through the internal integrated high-speed Ethernet bridge (G-Ethernet Bridge). The 4 low-speed Ethernet interfaces can also directly forward Ethernet frames through the low-speed Ethernet bridge (L-Ethernet Bridge). The low-speed Ethernet interface and the high-speed Ethernet interface can also directly forward Ethernet frames through the low-speed Ethernet bridge + DRE + high-speed Ethernet bridge. This method greatly reduces the delay time of data forwarding between Ethernet interfaces.

Figure 6: TC4xx Ethernet Bridge

In the Ethernet backbone network with central processing units and regional controllers as nodes, it is often necessary to transmit multiple Ethernet data frames. Some data needs to be transmitted deterministically (such as control data), some data will take up a lot of bandwidth (such as audio and video data, ADAS sensor data, etc.), and some are regular data (such as no requirements for transmission delay). Therefore, in this backbone network, Ethernet frames need to be classified. For control data, it must be ensured that it can be sent out within a controllable delay time. For audio and video or ADAS sensor data, it must be ensured that during normal transmission, it cannot interfere with the transmission of other Ethernet frames in the network, causing other high-priority Ethernet frames to be blocked.

The Ethernet TSN protocol solves this problem very well. IEEE802.1Qav implements traffic shaping, priority division and queue management, which solves the problem of data conflict very well. On this basis, IEEE802.1Qbv implements the time-aware Shaper mechanism, which allows the port to control whether the traffic is allowed to be transmitted according to a certain time base. The transmission switch is controlled by the transmission gate and the gate control list (GLC). Through this time slot division mechanism, the time-sensitive message flow and other ordinary message flows are isolated, which can not only realize the deterministic transmission of time-sensitive messages, making the message arrival time predictable, but also avoid the interference of ordinary messages and improve real-time performance. IEEE802.1AS provides a time synchronization mechanism for each node in the Ethernet network. On this basis, IEEE802.1AS-rev adds the concepts of master clock redundancy and multiple time domains.

The AVB/TSN protocols supported by the TC3xx/TC4xx Ethernet controllers are as follows:

Figure 7: TC3xx/TC4xx Ethernet TSN Support

*1) IEEE802.1 Qbv-prelim: refers to the support of a slot function in the channel/queue of TC3xx's GETH. For example, a synchronization cycle can be divided into 3 slots, and then 3 queues can be configured, each queue occupies one slot, so that the 3 queues can send different Ethernet frames and the data sent by the 3 queues will not interfere with each other.

3. Non-interference

In the regional centralized architecture, the number of ECUs will be greatly reduced. Some of these reduced ECUs will be incorporated into the regional controllers, while others will upload their control functions to the central processing unit and transform themselves into smart sensors or smart actuators. In this process, the regional controller will carry more and more functions, and it is crucial that each function runs independently and does not interfere with each other.

By core

At present, multi-core MCUs have been widely used in automotive electronics. Each core can be assigned a function, so that each function runs in parallel, improving operating efficiency and ensuring that they do not interfere with each other. Of course, this requires relying on the Memory Protection Unit (MPU). TC3xx/TC4xx has up to 6 CPU cores, and each CPU supports the Memory Protection Unit (MPU). Taking TC3xx as an example, each CPU core has 6 groups of protection settings, each of which has 18 data protection areas and 10 code protection areas. After configuring the code data and code protection areas, other CPUs will not be able to access these areas. In addition, consider the situation where an operating system is running in a CPU. When multiple tasks are executed simultaneously, a set of protection settings can be assigned to each task, so that data and code can be isolated between tasks.