About the test requirements and application analysis of audio and video SoC

The convergence of the consumer sector is accelerating, and the boundaries between consumer computers and communications applications are becoming more blurred as each device continues to add new features. For example, a wireless cell phone, a single device now has built-in digital video, video, Internet and email access, multimedia messaging, MP3 players, location services, PDA capabilities, and even broadcast MTV.

The emergence of high-quality audio and video applications in wireless mobile phones requires faster sampling rates, wider dynamic range, and larger memory. Even in the limited space of a car, a global positioning system (GPS) receiver that stores DVD information and stores multi-channel audio and high-resolution location display requires high-quality audio and video.

The convergence of consumer applications highlights the importance of system-level integration, which is the integration of RF, mixed signals, high-speed interfaces, power management, memory and high-performance processors. In order to reduce the size, cost and power consumption, such devices are made of system-on-chip (SoC) or single-package system. With the increase in functions and various cores, the number of pins is also increasing to meet the requirements of digital control lines and data lines.

As SoCs and SIPs in high-volume consumer industries become more complex, the conflict between the two basic requirements of low cost and high device life cycle becomes more prominent. Consumers demand improved performance at the same or lower cost, and often propose new improvements. Therefore, components must be thoroughly tested at low cost and extremely quickly.

While greatly reducing the throughput overhead of the ATE architecture, it can provide more parallel processing capabilities in testing, which may properly solve the additional time problem caused by testing increasingly complex devices. In order to solve the emerging analog core problems in cutting-edge consumer devices, in addition to the above two measures, the resolution and accuracy of ATE hardware must be guaranteed.

Simple 10-bit effective resolution and 4KHz bandwidth can meet the audio quality requirements of early wireless phones. The latest development trend shows that the device can support CD-quality audio performance, stereo and surround sound effects with stricter specifications. The market claims to have 24-bit audio resolution, but the actual effective performance is generally 16-bit to 17-bit, equivalent to a dynamic range of 98dB to 104dB and a bandwidth of 20KHz.

When discrete CD-quality DACs and ADCs were used in consumer applications, the ATE-related test costs were manageable because they had the initiative to increase device prices. However, when CD-quality cores were integrated into SoCs, the increase in device prices could no longer compensate for the increase in ATE test costs due to the increased test time and negative impact on the cost of test (COT) caused by the additional functions.

For mixed signal dynamic testing, it is crucial to prevent spectrum leakage in the spectrum generated during the analysis process. Therefore, the following relationship must be satisfied: M/N=Ft/Fs. In the formula, M is the number of capture cycles; N is the number of sampling points; Ft is the test signal frequency; and Fs is the sampling frequency.

For low-fidelity audio devices, such as microphones with ADC input or headphones with DAC output, an 8KHz sampling frequency is used, which is equivalent to a 4KHz bandwidth. If the test signal frequency is 1.03125KHz, 66 cycles can be captured relative to an 8KHz sampling frequency and 512-point acquisition. The sampling time is equal to the number of sampling points divided by the sampling frequency, which is 64ms. Audio testing requires more than 10 tests, including multiple gain states; idle channel noise (ICN), crosstalk (XTALK) and intermodulation distortion (IMD). In this way, even for a simple core, the total test time is 650ms.

The test overhead of transferring 20 bits of sampled data from the ATE's analog or digital capture memory to the workstation is also considerable. To determine the amount of data transferred for analysis, multiply 20 bits by the number of sample points N, and then multiply by the number of test measurements of the test core. In this example, 20 bits × 512 points × 10 measurements totals 102,400 bits. Assuming a 1MB bandwidth between the analog module and the workstation, the transfer time to test the DAC core is approximately 100ms. The digital capture memory transfer overhead is also 100ms at the same bandwidth. Therefore, for voice quality DAC and ADC testing, a 200ms transfer overhead increases the total test time to 1500ms (650ms + 650ms + 200ms).

To further illustrate this problem, consider the impact of a surround sound audio processor on test time. AC3 digital audio provides 6 analog outputs: front L/R; surround L/R; center speaker and subwoofer. From an analog point of view, these devices require a combination of high dynamic range and parallel testing.

CD quality dynamic range and bandwidth require a higher sampling rate. Using the above formula and substituting Fs=4.8KHz, the sampling time is 10.7ms. Taking into account hardware setup, test stabilization and other overhead, the test time is 15ms. Taking into account the number of measurements more than 10 times, the total test time rises to 150ms. This means that for each position 6 channels, the serial test implementation will take 900ms.

The test point implementation scheme can fully utilize the advantages of parallel testing of multiple waveform digitizers. However, data transmission is still serial in multi-test point testing, and the transmission overhead is cumulative. Therefore, even if 4 waveform digitizers are used, the 4-test point test implementation scheme requires 900ms+4×600ms=3300ms.

Wireless devices have set multiple standards in the same mobile phone. To support these standards, chipsets often have redundant baseband analog converters and RF transceivers. For example, in audio surround sound processors, the numerous analog cores in wireless baseband processors have a huge impact on test time. The main challenge in testing these devices is how to set up sufficient parallel tests in the analog test hardware to obtain the efficiency of multiple test points.

The baseband processor block consists of a quadrature (I/O) transmit (TX) DAC and receive (RX) ADC pair. In 2G to 2.75G GSM/GPRS/EDGE technology, the carrier channel spacing is limited to 200KHz, resulting in a low-frequency zero IF. W-CDMA uses a 5MHz channel, which corresponds to a wider bandwidth.

The RX and TX paths usually require full dynamic testing, including signal pair distortion (SND), CIN, and XTALK. I/Q pairs of DACs and ADCs also require gain matching and phase matching testing, with specifications specified within 0.1dB and 3 degrees of high accuracy, respectively. The requirement to ensure channel isolation during transmission leads to additional out-of-band (OOB) attenuation testing of the DAC. Adjacent channel power ratio (ACPR) can confirm the degree of channel isolation, and for W-CDMA DACs, the OOB frequency is tested up to 10MHz.

Current SoC devices support a variety of video input standards. Traditional NTSC or PAL devices have super video CS-VIDEO and composite analog outputs. Supporting HDTV requires three additional outputs to provide signals that comply with YPrPbHDTV (EIA-770.1-3). To prepare all the above outputs, six video DACs are required: two for S-Video, one for composite output, and three for RGB.

Although the digital video standard requires a maximum interface speed of 74MHz, the analog bandwidth required to test DAC performance is about 8MHz and the resolution is 10 to 12 bits. Typical test items for a single video DAC include integral nonlinearity (INL), differential nonlinearity (DNL), and SND measurements. The picture quality of the HDTV system is determined by the relative accuracy of the DAC output, and additional tests must be performed on the output gain and phase matching. The total test time of the built-in digital video device is directly related to the number of parallel digitizers available for testing. The number of video DACs to be tested is usually more than 6, and due to the lack of tester resources, it is essential to establish a serialized test solution.

Although reducing the total COT is affected by many variables, implementing multi-site testing and parallel testing to improve throughput is undoubtedly the main method. The latest generation of ATE systems uses a multi-port architecture that supports grouped tester resource structures that match the functions of the device under test.

The two main functions that achieve this are the per-port timing generator, which matches the frequency of the test core, and the per-port sequencer, which can work in different test modes and automatically execute sequence instructions. The multi-port per-pin solution goes a step further and breaks down the granularity of both digital and analog resources of the ATE system to each pin. Examples of the necessary resource structures for testing a typical SoC include: DSP used as a communication processor, memory, and ADCs and DACs that interface with the analog IF or RF front end. In this case, the digital pins are configured in scan mode to test the DSP core.

The ADC block requires an arbitrary waveform generator (Arb) and digital channels in capture mode to collect and analyze the ADC output. The DAC requires multiple digital channels consisting of ports, which are tested using a digital source memory (DSM) or waveform memory segment and a waveform digitizer. Each port can automatically operate at different test frequencies and execute different sequence instructions.

Since the test system is segmented on a per-pin basis, the application software can automatically manage most of the control of multiple test points by replicating the image of the test vector and the sequence on the pins used by each test point. Concurrent testing is an extension of multi-port testing, allowing these cores to be tested in parallel. Of course, each core in the device should be independently accessible and controllable by the ATE system and able to work independently. Modifying the pure sequence flow of serial testing of each device core to a sequence flow of parallel testing of multiple device cores can greatly reduce test execution time.