Learn more about Soitec’s SmartSiC technology

Preface

There are very good reasons to adopt silicon carbide (SiC) in the inverters of electric vehicles. When replacing traditional silicon-based inverters, SiC solutions will bring about 5-10% efficiency improvements. This means that more power is delivered to the motor instead of being wasted in the DC-AC power conversion process. Although there is a cost to making this transition, it can be more than paid for by reducing the vehicle's expensive, bulky lithium batteries. As a result, automakers around the world are developing SiC inverters, and the demand for silicon carbide (SiC-MOSFET) and the key silicon carbide substrates themselves has never been greater. According to multiple analysts, the SiC market will be worth $1-2 billion in 2023 and grow at a compound annual growth rate of 30%. However, some important questions remain about the future of this emerging industry. The most worrying is the cost and supply of silicon carbide substrates. Although Wolfspeed, Coherent and others have announced increased wafer supply in the near future, the availability of materials remains a challenging limitation for the industry, resulting in long lead times and high costs.

Additionally, Tesla, which initially sparked the SiC craze with the launch of the Model 3 in 2017, announced that they would reduce the amount of SiC used in future low-cost, low-power vehicles. This can actually be seen as a positive: it finally indicates that SiC MOSFETs will be used in low-power, mass-produced electric vehicles, whereas SiC has been mainly limited to the high-power/luxury car segment to date. However, given that the solution is rumored to be a hybrid Si IGBT – SiC MOSFET solution (although all SiC solutions have value), automakers are still under pressure to reduce the cost of SiC chips. Cost analysis by PGC Consultancy and Exawatt shows that substrates account for 40-50% of the cost of the finished chip, and the market needs to find cost reductions in this most basic material.

Given the scarcity and cost of SiC substrates, it is no surprise that Soitec’s SmartSiC product is one of the most discussed topics in the market, along with Wolfspeed’s transition to 200mm and the rise of Chinese players in the market. In a deep dive into Soitec’s SmartSiC product, we set out to explain what it is, the potential impact it could have on device technology and costs, and what the main challenges facing its technology and operating model are.

SmartCut process overview
As shown in the figure below. The process was first proposed in 1997 and starts with two traditional Si substrates, one is the base (handle) substrate and the second is the donor (donor) substrate, which attaches the thin device layer to the final SOI stack. First, the donor substrate is oxidized to form a buried oxide on its surface. Then, hydrogen is implanted into the same surface of the donor substrate, and the hydrogen atoms stay at a shallow distance below the oxide, equivalent to the thickness of the device layer. The donor wafer is then cleaned and flipped so that its oxidized and hydrogen-implanted surface can contact the base substrate. The room temperature affinity wafer bonding process temporarily fuses the two wafers, and then annealing causes the implanted hydrogen to expand, splitting the donor substrate, so that the device layer and buried oxide remain on the base substrate. After high temperature annealing to achieve permanent bonding, CMP polishing completes the SOI wafer. The rest of the remaining donor wafer can be reused for the next SOI wafer after its surface is smoothed by CMP polishing.

Soitec turns to silicon carbide

After more than two decades of producing SOI substrates, Soitec announced in 2019 that they would apply their Smart Cut process to SiC to produce "engineered substrates" to address "challenges associated with the supply, yield and cost of silicon carbide substrates". Details of Soitec's SmartSiC process were announced in 2021, and in 2022 Soitec and STMicroelectronics announced that they were "collaborating" and that STMicroelectronics would qualify wafers within 18 months of the announcement.

Soitec showed off their SmartSiC substrates. In summary, these consist of a thin layer of single-crystal SiC permanently bonded to a (relatively) low-cost, highly doped, multicrystalline SiC handle substrate (probably provided by Mersen). The SmartSiC substrate manufacturing process is shown in the figure below. Soitec reused their SOI schematic, replacing the single-crystal SiC donor wafer and multicrystalline SiC handle wafer with silicon wafers. This helps to compare to the Smart Cut(TM) process: a single-crystal SiC wafer is implanted with a light element (probably hydrogen), then cleaned, flipped, and bonded to a handle wafer. Two anneals, the first at a lower temperature to break the donor wafer, and the second at a higher temperature to make the bond permanent, leave the SmartSiC substrate and the bulk of the SiC substrate ready to be polished and reused.

In response to our questions, Soitec confirmed that the carbon side of the single SiC is bonded to the handle wafer, ensuring that the SmartSiC surface is a single SiC Si side - the same as a conventional SiC substrate. The single-crystalline SiC layer (which we assume is about 1μm thick) bonded to the polycrystalline SiC surface should be a suitable seed layer for growing conventional epitaxial layers on its surface, followed by device fabrication.

Potential advantages of SmartSiC substrates

One of the most significant advantages of using the SmartSiC process is the ability to reuse a single single SiC wafer, at least 10 times according to Soitec, which helps solve the SiC material supply issues currently facing the industry. However, Soitec seems keen to convey the message that this does not necessarily mean that their wafers will become cheaper as a result.

In contrast, Soitec argues that they have a superior product, based on the advantages of SmartSiC substrates, which minimize substrate-related resistance. They claim that the impact on the substrate will have a significant impact on reducing the total device resistance (Rds,on), allowing for smaller chips at a given resistivity. As we discussed previously, smaller chips mean more products can be produced on each wafer, with slightly higher yields, reducing the cost per chip and increasing fab capacity.

To understand the potential substrate resistance improvements, it is worth recalling its role in SiC power devices, such as the planar MOSFET in the figure below. The power device is arranged vertically, with the high-voltage drain terminal on the back side of the substrate. This arrangement maximizes the current density of the device, but it requires the electrons to pass down through the thin drift region and then through the substrate before reaching the drain.



As a result, the substrate is the largest contributor to chip cost and has considerable resistance, playing almost no active role in the device. During front-end manufacturing, the 350 µm substrate provides mechanical support for the 5-10 µm epitaxial device layers. However, after this, it is thinned to 100-180μm (depending on the manufacturer and generation) before the drain metal contact is deposited, minimizing the impact of substrate resistance. In a 750V MOSFET, with a drift region thickness of only 6-8 µm, the substrate will contribute up to 17% of the total device resistance.

When conventional single-crystal SiC substrates are grown by seed sublimation, there is a fundamental trade-off between crystal quality (low defect density) and doping density (low resistivity). Since the substrate is the basis for subsequent epitaxial growth, the quality of the substrate cannot be compromised, so its resistance is relatively high (typically 15-25 mOhm-cm). The limited doping density of the substrate also adds to the small contact resistance (Rc) between the substrate and the drain. In contrast, when producing multicrystalline silicon carbide substrates, their defect density is not critical, so their doping density can be pushed to the limit, thereby minimizing their resistance.

Previously, Soitec has been reluctant to reveal much about its wafer specifications, only mentioning the maximum value of its resistivity in marketing. However, recently at CS International 2023 in Brussels, Soitec showed for the first time "typical" values ​​for its substrates, as shown in the figure below. According to this, typical polycrystalline SiC resistivity is 2.5 mOhm-cm, with a bonded interface adding 10 µOhm-cm2 to the resistivity. They also said that high doping almost eliminates contact resistance, reducing it from 50-100 µOhm-cm2 to 5 µOhm-cm2.

The values ​​Soitec claims for reduced back contact resistivity come from a presentation to ICSCRM in 2022. They found that the contact resistivity of a non-laser annealed SmartSiC substrate was 10 times lower than the same contact resistivity of a laser annealed standard single crystal silicon substrate. They therefore suggest that the laser annealing stage can be eliminated, removing a back-end manufacturing cost.

Finally, in response to my question, Soitec claims they are able to achieve a flatter substrate and shared data showing lower SFQR values ​​compared to single SiC. While this will aid processing and potentially improve yields, the benefit is not quantifiable for the model in this article.

Analyzing the cost benefits of SmartSiC substrates

A techno-economic model created jointly by PGC Consultancy and Exawatt translates improvements in device technology and supply chain into the cost of a finished chip. This cost covers substrate, epitaxy and manufacturing costs, and considers yield related to defect density (epitaxial yield) and device manufacturing (chip yield). In this section, we apply the modeling to Smart Cut(TM) wafers to evaluate their potential benefits. The model uses as a benchmark a state-of-the-art commercial 15 mOhm 750V Trench SiC MOSFET formed on a conventional single SiC substrate thinned to 140 µm. Against this benchmark, we model the same device implemented on a SmartSiC substrate using Soitec’s typical substrate and contact resistivity values, as shown in the figure below.