Astera Labs Enters Pre-Production of Leo Memory Connectivity Platform for CXL Add-On Memory Expansion and Pooling Applications

Astera Labs Enters Pre-Production of Leo Memory Connectivity Platform for CXL Add-On Memory Expansion and Pooling Applications

Solving memory bottlenecks and composability in accelerated and intelligent infrastructure, laying the foundation for cloud-scale deployments

Beijing, China - September 1, 2022 - Astera Labs, a company dedicated to intelligent system connectivity solutions, announced today that it has begun to provide pre-production samples of the Leo Memory Connectivity Platform to customers and strategic partners. The platform supports Compute Express Link™ (CXL™) 1.1 and 2.0 to achieve security, reliability and high-performance memory expansion and pooling for cloud servers. This milestone was achieved after successful end-to-end interoperability testing of Leo Smart Memory Controllers with the industry's leading CPU/GPU platforms and DRAM memory modules on a variety of real-world workloads.

“Our Leo Memory Connectivity Platform supporting CXL 1.1 and 2.0 is purpose-built to address processor memory bandwidth bottlenecks and capacity limitations in accelerated and intelligent infrastructure,” said Jitendra Mohan, CEO of Astera Labs. “We have achieved a significant industry-first milestone by successfully delivering our Leo intelligent memory controller, Leo-based hardware board solutions, and comprehensive software tools to our partners and customers, paving the way for seamless, large-scale deployment of memory pooling and scaling in the cloud.”

The CXL standard has proven to be a key enabler for the realization of artificial intelligence (AI) and machine learning (ML) in the cloud. The Leo intelligent memory controller implements the CXL.memory (CXL.mem) protocol, allowing the CPU to access and manage CXL attached memory to support general computing, AI training and inference, machine learning, in-memory databases, memory tiering, multi-user use cases and other application-specific workloads.

The Leo intelligent memory controller supports cloud-scale deployment of compute-intensive workloads such as AI and ML, providing the comprehensive capabilities required by hyperscale data centers. Leo provides server-level customization in reliability, availability, and serviceability (RAS), helping data center operators customize personalized solutions to prevent factors such as memory errors, material degradation, environmental impacts, or manufacturing defects from affecting application performance, uptime, and user experience. The use of extensive remote diagnostic capabilities and software APIs for fleet management facilitates large-scale management, debugging, and deployment on cloud-based platforms. Unlike other memory expansion solutions, Leo supports end-to-end data path security, unleashing maximum capacity and bandwidth, providing up to 2TB of memory per Leo controller and up to 5600MT/s per memory channel, which is the minimum speed required to fully utilize the bandwidth of the CXL 1.1 and 2.0 interfaces.

“CXL is an open standard interface that enables composable memory infrastructure, scaling and sharing memory resources to bring greater efficiency to the modern data center,” said Raghu Nambiar, vice president of Data Center Ecosystem and Solutions at AMD. “We are honored to have worked closely with Astera Labs to develop the Leo Memory Connectivity Platform and validate its interoperability and reliability with AMD processors and accelerators.”

The Leo smart memory controller has a flexible memory architecture. In addition to the JEDEC standard DDR interface, it can also support other memory vendor-specific interfaces, providing unique flexibility and supporting different memory types to reduce the total cost of ownership (TCO). The Leo smart memory controller is also the industry's first solution to solve the problem of memory pooling and sharing, which can improve the memory utilization and availability of data center operators, thereby further reducing TCO.

“CXL provides a platform for a host of memory connectivity options and innovations in next-generation server architectures, which is key if the industry is to realize the vast potential of data-centric applications,” said Zane Ball, vice president and general manager of Intel’s Data Platforms Engineering and Architecture Group. “Our continued collaboration with Astera Labs, a CXL ecosystem provider, through the Leo Memory Connectivity Platform will help customers develop reliable, interoperable CXL memory expansion and pooling solutions.”

We worked closely with the industry’s leading processor vendors, memory vendors, strategic cloud customers, system OEMs and the CXLTM Consortium to develop the Leo Intelligent Memory Controller, ensuring it meets partner-specific requirements and interoperates seamlessly across the ecosystem.

“Astera Labs has been a valuable contributor to the CXL Consortium with its expertise in connectivity and efforts in vendor-neutral interoperability,” said Siamak Tavallaei, Chairman of the CXL Consortium. “It is exciting that Astera Labs is delivering a solution that will help the CXL memory expansion and pooling product market grow rapidly.”

Astera Labs Leo Memory Connectivity Platform for CXL add-on memory provides the following product solutions:

• Leo E-Series intelligent memory controller supports memory expansion

• Leo P-Series intelligent memory controller supports memory expansion, pooling and sharing

• Aurora A-Series Smart Memory Hardware Solution - PCIe CEM Add-in card for plug-and-play deployment of Leo Smart Memory Controller

Development and Evaluation:

Astera Labs publishes a wide range of product documentation, application notes, firmware, software, management utilities and development kits to enable partners and customers to seamlessly evaluate, develop and deploy Leo Smart Memory Controllers and Aurora A-Series Smart Memory hardware solutions.

Related resources:

• Leo Memory Connectivity Platform: First Look Demo

• Leo Memory Connectivity Platform unlocks the full potential of CXL

• Leo Memory Connectivity Platform Product Overview

• Leo Memory Connectivity Platform product page