Design of 1553B Communication Module Based on FPGA

The MIL-STD-1553 bus is a deterministic and reliable data bus developed by the U.S. Department of Defense. It is widely used in military aircraft, military vehicles, and shipboards. At present, there are two main ways to implement the 1553B bus interface module: one is to use a dedicated protocol chip (such as DDC's BU-61580, HOLT's HI-6110, etc.); the other is to use FPGA and CPU to implement the 1553B protocol module.

This system adopts the latter method. The hardware uses PowerPC chip PPC405EP and Xilinx FPGA chip XC3S200 as the core chip of the system, and uses VHDL language to implement the 1553B bus protocol. Compared with the method of using a dedicated protocol chip to implement the 1553 bus interface, this solution has a very low cost, is easy to expand functions according to needs, and is flexible to use.

1 1553 bus analysis

There are three types of devices on the MIL-STD-1553 bus: bus controller, remote terminal and monitor. The most important one is the bus controller (BC), which initiates all operations on the bus (controls data transmission on the bus by issuing different commands); the remote terminal (RT) receives commands from the BC and transmits data accordingly; the bus monitor (BM) receives and stores data on the bus.

The data interaction on the 1553B bus is based on the message mechanism. The standard defines 10 message transmission formats, and these 10 transmission formats all use the above three word types. The data transmission on the bus uses one of these 10 message transmission formats. The transmission process is as follows: BC sends a certain command word through the bus, all RTs receive the command word, and compare the address field in the command word with their own address. If they are the same, they receive the command word; then, RT parses the command word and completes the corresponding operations according to the command (receive data words, send data words, synchronize, self-test, etc.). These operations will generate corresponding status words and send them to BC. BC uses the status word to determine whether the RT is working properly. If the terminal address in the command word received by the RT is a broadcast address, all RTs receive the command, but do not return the status word to the BC.

2 System Design

2.1 System Structure

The system structure is shown in Figure 1. The 1553B protocol processing and encoding and decoding are all implemented by FPGA. The BC, BM and R/T functions are integrated on the same circuit, and the required functions can be selected through software settings. At the same time, it integrates communication and test functions, which can detect various possible errors and generate various errors according to test requirements.

The CPU chip uses AMCC's PowerPC405EP. This chip not only includes a high-performance RISC processor core, but also has an SDRAM controller, PCI bus interface, Ethernet interface, external ROM and peripheral resource control, serial port, IIC interface, general I/O port, etc., and supports DMA function.

The PXI interface in the system is implemented by using the PCI interface of PowerPC405EP and the external switch circuit expansion. The CPU communicates with the 1553 module through the EBC bus, and its interface circuit is implemented by FPGA. The interface circuit shown in Figure 1 mainly completes functions such as channel selection and data loopback. [page]

2.2 Overall Plan

The 1553B bus protocol is implemented by hardware and software. The overall design idea is that hardware and software use two methods, interruption and query, to exchange information through a shared data buffer. The following introduces the overall data transmission and reception process of the system. The software and hardware functions of this system are divided and implemented according to this process.

2.2.1 Data sending process

The upper-level software transmits control and data information to the hardware logic circuit in the form of a data structure, and the hardware circuit automatically sends the data to the 1553B bus according to the control information. When the CPU sends data to the hardware logic, it should first detect whether the last transmission has ended. The specific method is: read the channel status register transmission completion bit. If it is valid, it means that the last transmission has ended. Only when it is detected that the last transmission has ended can the data transmission operation be performed. After the hardware circuit sends the data, an interrupt request will be generated. The software queries the status register based on the interrupt request to determine the next operation. The transmission process is briefly described as follows:

(1) The CPU writes an instruction word/status word and error control information to the data transmission FIFO;

(2) The CPU writes a send enable signal to the channel control register;

(3) The CPU writes 0 to 32 times of data and error control information to the data transmission FIFO;

(4) The hardware logic detects the sending enable signal;

(5) The hardware logic automatically takes out the data stored in the FIFO in sequence;

(6) The hardware logic processes the data accordingly based on the error control information and sends the data to the 1553B bus;

(7) The hardware logic sets the send completion status bit and generates an interrupt signal 2 μs after the message is sent.

2.2.2 Data Receiving Process

After the hardware logic receives the data on the 1553B bus, it performs error detection on the data and combines the corresponding status information with the data and stores them in the receive FIFO. When the receive FIFO reaches a certain capacity, an interrupt signal is generated to the CPU. The CPU reads the FIFO and takes out the data and status. The receiving steps are as follows:

(1) Hardware logic receives data on the bus;

(2) Hardware logic performs error detection on the data and generates status information;

(3) The hardware logic writes the data and status information into the receive FIFO;

(4) When the receive FIFO reaches a certain capacity, an interrupt signal is generated;

(5)CPU responds to external interrupts;

(6) The CPU reads the FIFO and takes away the status information and data;

(7) The CPU analyzes the status information and decides how to process the data. [page]

3 FPGA Implementation of Bus Encoding and Decoding

The FPGA chip in this system uses Xilinx's Spartan-3A XC3S200. This series of products uses 90 nm technology, supports the industry's most extensive I/O standards (26 types), and has unique power consumption and configuration functions as well as anti-cloning security advantages.

All functions of FPGA are implemented in VHDL language, and its functional block diagram is shown in Figure 2. Its main tasks are: (1) Manchester code encoding and decoding, including serial/parallel conversion. (2) Parsing of 1553B protocol messages, including recognition of synchronization headers, recognition of various errors, parity check, etc. (3) Generation of 1553B protocol messages, including generation of synchronization headers, generation of various status bits, and generation of various error messages. (4) Implementation of CPU interface. (5) Implementation of various interrupt signals. (6) Timing and timeout control circuits, etc.

3.1 Bus transmission circuit implementation

If there is no requirement for error injection, the implementation of the encoder is relatively simple. It only needs to convert parallel data into serial data at a transmission rate several times higher than 1553B (this design uses 12 times the frequency) and add the corresponding synchronization header. In terms of hardware, the data transmission circuit mainly consists of a state machine, a dual-port FIFO, an injection error flag register, and a control circuit. The state diagram of the state machine is shown in Figure 3. After reset, the state machine detects whether there is data in the FIFO at the rising edge of each clock. If it is empty, it stays in the idle state. Once the upper-layer software writes data to the FIFO through the EBC interface, the hardware circuit automatically reads the data. Entering the synchronization header sending state, the hardware circuit sends the corresponding serial synchronization header according to the control word of the command register, and then enters the data sending state. At each clock edge, the shift register shifts the data of the data register out, encodes the data in the Mann code, and sends it out. At the same time, the data counter automatically increases by 1. When the count value is 16, it enters the parity check state, encodes the check bit obtained by XOR, and sends it out.

This system requires testing capabilities, mainly with the following requirements for injecting errors:

(1) EI_BITCOUNT: The number of bits of the data specified in the message is incorrect (not 16 bits);

(2) EI_PARITY: The parity bit of the specified data in the message is wrong;

(3) EI_SYNC: wrong synchronization header;

(4) EI_WORDCOUNT: Make the data length in the message not equal to the length in the command word;

(5) EI_MIDBIT: The specified data bit has a zero crossing error, which is 300 ns later than the expected position;

(6) EI_MIDSYNC: The zero crossing error of the synchronization head is 300 ns later than the expected position;

(7) EI_BIPHASE: There is no zero crossing during the entire bit time.

The hardware circuit requires that the corresponding circuit be added to the state machine to detect the flag bit in the error register and generate the corresponding error. [page]

3.2 Bus receiving circuit implementation

Both BC and RT need to parse the received data. The main functions of the receiving circuit are: Manchester code decoding, serial-to-parallel conversion, synchronization header detection, parity check and various error detection. As shown in Figure 4, the state machine enters the synchronization header search state after reset. The hardware circuit detects several synchronization headers at a frequency of 12 times the 1553 bus transmission rate. If the synchronization header is received, the corresponding bit in the status register is set and the data receiving state is entered; otherwise, it stays in this state. In the data receiving state, the shift register shifts the decoded data in at the clock edge. After the data counter counts to 16, it enters the parity check state; then, the data and status are written into the FIFO. The hardware circuit detects various errors at each stage of the state machine, and returns to the synchronization header search state if an error occurs. At the same time, an error flag and an interrupt signal are generated.

3.3 Implementation of Hardware Interrupt Function

As mentioned above, the communication between the system software and hardware is mainly carried out through information exchange through interruption and query. The hardware circuit implements the following interrupt functions:

(1) An interrupt is generated every time a command/status word is received;

(2) Data length counter interrupt and enable. The software parses the received command/status word. If there is data ready to be received, the data length value is written into the data length counter and the counter is enabled. When the hardware receives a data word, it decrements the counter until it reaches 0 and generates an interrupt. At the same time, the data counter interrupt is disabled.

(3) An interrupt is generated when the receive FIFO is half full or 3/4 full;

(4) The receive FIFO is full (overflow) and generates an interrupt;

(5) The transmit FIFO is empty and an interrupt is generated;

(6) Interrupt status/enable register;

(7) Wait for timeout interrupt (the length of received data is insufficient);

(8) The data counter is time-stamped at the interruption point; each command/status word received is time-stamped; the synchronization header of the sent command/status word is time-stamped at the zero crossing point. [page]

4 Software Design

The software design includes the design of the onboard embedded program and the host driver. The onboard embedded program and the host driver complete data interaction by sharing the PPC plug-in memory, and the onboard embedded program completes hardware operations and data transmission and reception by accessing the registers and FIFOs of the FPGA. Its structure is shown in Figure 5.

The host driver development platform is LabWindows/CVI, which provides users with convenient and practical API interface functions and their definitions.

The development platform of the embedded program is Tornado2.2. The program mainly completes the initialization of the module, the message parsing of each channel BC\\RT\\BM, the interrupt service processing, the interaction with the host, etc. Among them, the message parsing is the core part of the embedded program.

When the module option is a multi-function module, each channel is required to work as a BC, BM and up to 31 RTs at the same time during the same working period. When the available terminals of the system under test are limited, and sufficient and complete tests are desired, the multi-function module will provide sufficient terminals for testing. In order to simultaneously and correctly play the three different roles of BC, BM, and RT, the embedded program design of the module introduces the state machine design concept of programmable logic design. BC, BM, and RT each have their own state machine.

5. Tests and Conclusions

Figure 6 shows the waveform diagram of the 1553 transceiver simulation. Due to space constraints, only some functions are shown. The simulation mainly verifies the following process: the software writes the three data to be transmitted and the corresponding control word into the FIFO through the EBC bus interface, and converts them into serial data through the hardware circuit and outputs them to the differential output end; the output is looped back to the differential input end, and is written into the FIFO again through the decoding circuit, generating an interrupt signal, and the data and status are read back by the software through the EBC bus.

After simulation and actual verification, this system meets the requirements of 1553B bus protocol. At the same time, this design has become a product and has been applied in practice. [page]

References

[1] Condor Engineering Inc. MIL-STD-1 553 Tutorial[Z].2000.

[2] Data Device Corporation． MIL-STD-1 553 DESIGNER'S GUIDE[Z].1998.

[3] Applied Micro Circuits Corporation.PowerPC 405EP Embedded Processor datasheet[EB/OL].http://www.appliedmicro.com/MyAMCC/retrieveDocument/PowerPC/405EP/PPC405EP_DS2003.pdf, 2003.

[4] Xilinx INC. Spartan-3 FPGA Family: Complete Data Sheet [EB/OL]. http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf, 2008.