Compiled from allaboutcircuit
With the advent of the Internet of Things and the proliferation of small, battery-powered products, edge computing has become a dominant area of the electronics industry. New requirements for these low-power, high-performance edge devices are forcing engineers to reimagine computing and device management.
How will edge computing design develop in the next few years? Robert Oshana, vice president of software engineering research and development at NXP, provides special development trends that should be paid special attention to when designing edge devices.
Trend 1: From single-core to multi-core
One of the biggest challenges of edge computing is achieving both high performance and low power consumption for intensive applications like ML. Historically, engineers have relied on Moore’s Law and increasing clock frequencies to achieve better performance and lower power consumption—but this is no longer the case.
At the edge, higher frequencies mean more power consumption; engineers must find new computational methods to save power. Low-power applications can use energy harvesting to achieve long-term power delivery. However, another more common approach is to move from a single-core architecture to a multi-core architecture.
Single-core and multi-core processor architectures.
“You can’t keep increasing the frequency of a device, especially in embedded systems or wearables. So over the last decade, we stopped using processor architectures that had a single core and a high frequency. Instead, we chose to use many cores and reduce the frequency, which means less power,” Oshana explained. “The work still gets done, but the programming model changes. You have to distribute the computation across multiple cores.”
The idea is that using multiple parallel cores at lower frequencies can achieve the same computing performance as a single core at higher frequencies. The difference, of course, is that multi-core architectures can achieve lower power consumption for the same performance.
Trend 2: Dedicated Accelerators
Another emerging trend in edge computing is the increased use of hardware accelerators.
For unique computing tasks such as machine learning, general-purpose processing units are not utilized efficiently enough, especially as Moore's Law slows. Instead, researchers and engineers realized that they could get better performance and power by using hardware accelerators optimized for individual tasks, such as multiplication and accumulation.
The edge computing MCU architecture consists of various application-specific hardware blocks.
“Edge computing has to focus on three things: performance, memory, and power,” Oshana said. “Hardware accelerators, such as machine learning accelerators or GPU/DSP, can perform operations much faster, so you can optimize performance. Machine learning has its own set of complex algorithms that require hardware to accelerate it, and it also requires compilers to optimize the algorithms.”
Oshana said today’s shift toward machine learning accelerators is comparable to the introduction of digital signal processing (DSP) in the 1990s.
“Digital signal processors with long instruction word architectures became commercially available, and then optimizing compilers came along to go with them,” Oshana said. “In machine learning, I see exactly the same thing happening. It has its own set of complex algorithms that require hardware to accelerate it. It also requires compilers—in this case, compilers like Glow—to optimize the algorithms. You’ll see it continue to evolve in exactly the same way as with DSP.”
However, one challenge with this trend is that there is currently no consensus on the best type of hardware accelerator. For this reason, the industry is flooded with hundreds of startups that offer their unique approach to hardware acceleration. In the future, only a few of these startups will eventually win out, and the industry will consolidate to focus on a few accelerators.
Trend 3: Security Equipment Lifecycle Management
The third trend in the edge space is the increasing importance of device lifecycle management, especially in terms of security. IoT devices are often designed to be deployed remotely in the field and ideally can be operated without human intervention for many years, which complicates remote device management.
“You might want that device to be connected to the cloud – to replace software upgrades that are done on the device in the field. For more than a decade, you might want to update the software once a year via an over-the-air update, and you have to do that in a secure way.”
The solution to this challenge needs to start at the hardware level before deployment at scale. “The hardware components allow you to store private keys and communicate, and it also includes support for different forms of security software to handle the communication and connectivity.”
Some specific hardware security features include secure boot and secure processing. Security protocols for wireless and cloud communications are also increasing. If you want to decommission an edge node that is no longer in use, you must erase all proprietary or private information.
SoC Security Lifecycle Management
“In hardware, there are a number of ways we can zero out the RAM and ROM so that a hacker cannot access any code or firmware on the device,” Oshana explained.
“For device lifecycle management, you need different levels of security,” Oshana said. “Sometimes this is called a ‘defense-in-depth model,’ where you have different levels of security. It includes things like secure boot, secure processing, and the TrustZone architecture and Secure Enclave on the device.”
He continued, “When you communicate with the cloud, you’re doing it using secure protocols. And there’s a security model for every part of the device lifecycle. That’s what we call device lifecycle management.”
The future of edge design is changing
For engineers entering this field, it will be important to be able to cope with dynamic and changing challenges. Learning skills such as hardware/software security, heterogeneous computing, and low power consumption will undoubtedly be crucial for future edge hardware engineers. In addition to this, future engineers should be prepared to be fast learners because the field is developing rapidly and big changes may occur in a year.
Emerging IoT protocols such as Matter may also be standardized to support different protocols such as Bluetooth and Zigbee. Oshana also predicts that new protocols for high-power applications such as 5G will be more easily accepted. For example, a protocol called Red Cap New Radio (Lightweight 5G) may further develop the landscape of NR devices and generate more 5G use cases.
Oshana concluded: “Edge computing will grow because we can no longer do everything in the cloud. To optimize edge processing, we need to improve the way we build hardware and software systems.”
He added: “Edge technology communicates up to the cloud and down to the nodes. These small devices sit in the middle, so both architectures have to be coordinated. So it presents unique challenges.”
Previous article:The first TSMC WoW 3D packaged chip is mass-produced, and Graphcore Bow IPU is launched
Next article:RISC-V AI chips will be everywhere
- Popular Resources
- Popular amplifiers
- Let’s talk about the “Three Musketeers” of radar in autonomous driving
- Why software-defined vehicles transform cars from tools into living spaces
- How Lucid is overtaking Tesla with smaller motors
- Detailed explanation of intelligent car body perception system
- How to solve the problem that the servo drive is not enabled
- Why does the servo drive not power on?
- What point should I connect to when the servo is turned on?
- How to turn on the internal enable of Panasonic servo drive?
- What is the rigidity setting of Panasonic servo drive?
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
- LED chemical incompatibility test to see which chemicals LEDs can be used with
- Application of ARM9 hardware coprocessor on WinCE embedded motherboard
- What are the key points for selecting rotor flowmeter?
- LM317 high power charger circuit
- A brief analysis of Embest's application and development of embedded medical devices
- Single-phase RC protection circuit
- stm32 PVD programmable voltage monitor
- Introduction and measurement of edge trigger and level trigger of 51 single chip microcomputer
- Improved design of Linux system software shell protection technology
- What to do if the ABB robot protection device stops
- Let’s talk about the “Three Musketeers” of radar in autonomous driving
- Why software-defined vehicles transform cars from tools into living spaces
- How Lucid is overtaking Tesla with smaller motors
- Wi-Fi 8 specification is on the way: 2.4/5/6GHz triple-band operation
- Wi-Fi 8 specification is on the way: 2.4/5/6GHz triple-band operation
- Vietnam's chip packaging and testing business is growing, and supply-side fragmentation is splitting the market
- Vietnam's chip packaging and testing business is growing, and supply-side fragmentation is splitting the market
- Three steps to govern hybrid multicloud environments
- Three steps to govern hybrid multicloud environments
- Microchip Accelerates Real-Time Edge AI Deployment with NVIDIA Holoscan Platform
- Power amplifier driving capacitive load case sharing
- Power supply zero and live wire detection
- RSL1 Bluetooth characteristic value reading and writing
- Sapphire on PCB---DFM about optical positioning points
- How to choose between different chips in TI's Sub-1GHz product line?
- Design of optimal horn antenna based on HFSS
- Compilation and use of rocket-chip tool chain
- How to connect several cameras to a 100M switch
- Operational issues of XDS100V3.0 emulation motoware built-in project
- [Show goods] + Water Group Wholesale Department