How to improve the operating efficiency of domestic PLC and shorten the execution time when completing the same task

How to improve the operating efficiency of domestic PLCs and shorten the execution time to complete the same task. Let lower performance products complete higher performance processing requirements

1. When you can use a "word" (such as VW unit), try to avoid using a "double word" (VD unit). When you can use an integer, try to avoid using real numbers/floating point numbers.

2. Give priority to the use of surplus (other than hardware connections) IB, IW, ID, QB, QW, QD, followed by M and S;

3. Reduce unnecessary network scanning, and classify the networks that can be executed conditionally (especially AIW and AQW) into subroutines for conditional calls (such as timed interrupts);

4. Under the premise of ensuring process requirements, appropriately reduce the frequency of interruptions;

5. The subroutine should minimize the number of conditional judgments and standardize the subroutine import and export parameters to reduce code redundancy.

6. If SM0.0 is connected in series with other signals, it will only increase the program size and execution time, and will have no other effect (if the network already meets the required contacts on the left, there is no need to connect SM0.0 in series);

7. For subroutine calls with less input data, you can first determine whether the input data has changed. If there is no change (the comparison method can be referred to the 48th floor), you can directly skip the subroutine to reduce the scanning cycle.

8. Reasonable use of immediate IO instructions (minimize their use) can save the conversion time of domestic PLCs in processing immediate instructions.

9. Try to use calculation result memory instead of transition memory during calculation.

10. Avoid data type conversion. When necessary, use AC to store intermediate variables to reduce the number of conversions. Or reserve storage space when programming. For example, when using VW2 to store integers, leave VW0 empty and access the data in VW2 directly in the form of VD0.

11. Use the XOR instruction to implement the inversion of any bit (this instruction is slightly difficult and requires careful alignment during debugging);

12. For repetitive and time-consuming tasks, periodic processing should be adopted, including: allocating the initialization work to multiple cycles. Make the sampling time of multiple PID loops slightly different to avoid multiple interrupt calls in the same cycle, making the scanning cycle more uniform and stable.

13. Try to arrange the bit variables in the V area in V511.7, and arrange the frequently used VB/VW/VD variables in V4095, which can shorten the program scanning cycle.

14. When there is no need to share signals, multiple instructions placed in the same network will generate additional stack operations (which can be converted into STL for analysis), which will also increase the program size and execution time. The only benefit is that it is more compact in one network.