Asynchronous ASI/SDI signal electrical multiplexing optical transmission equipment based on CPLD

introduction

In recent years, with the rapid development of computer, digital network and television technology, people's demand for high-quality television images has been increasing, and China's radio and television industry has been changing with each passing day and developing rapidly. The digital TV satellite broadcasting launched four years ago has now formed a considerable scale. Equipment such as digital recording, digital special effects, non-linear editing systems, virtual studios, digital broadcast vehicles, network hard disk arrays, and manipulator digital playback systems have been gradually introduced into CCTV and provincial and municipal TV stations. Standard high-definition digital television SDTV/HDTV has been listed as a major national scientific research industrial engineering project, and trial broadcasts have been carried out on the Central Radio and Television Tower. At present, China's digital TV program production and digital TV terrestrial broadcasting are being vigorously promoted, and the "Eleventh Five-Year Plan" will be the preparation period for the overall translation of China's digital television, and it is an important stage for the transition of radio and television systems from analog to digital.

This design is designed to respond to this trend and meet the huge market demand for multi-channel ASI/SDI digital video signal optical transmission equipment. It is an optical transmission device that uses time division multiplexing technology to simultaneously transmit two channels of ASI/SDI digital video signals in one optical fiber. This design can lay a good foundation for the future development of more channels and higher-speed asynchronous digital signal optical transmission equipment.

System Implementation Solution

The working principle of the ASI/SDI signal optical transmission equipment is shown in FIG1 .

Figure 1 System Schematic Diagram

As shown in Figure 1, the ASI/SDI serial signal is shaped after passing through the equalization circuit and converted into a set of differential signals; the clock in the signal is then extracted through the clock recovery circuit for use in the subsequent decoding and synchronization signal; after passing through the decoding circuit, the serial high-speed signal is converted into a parallel low-speed signal to prepare for the subsequent electrical multiplexing process; finally, the asynchronous signal is synchronized with the local electrical multiplexing clock through the adjustment of the FIFO circuit, thereby realizing local electrical multiplexing; and then the signal is transmitted to the receiving end after electrical/optical conversion through the optical module. After receiving the signal, the receiving end recovers the original ASI/SDI serial signal after a series of inverse conversion circuits, completing the entire transmission process.

The electrical multiplexing technology of ASI/SDI signals in this design is the key to the entire technical link. Since the ASI/SDI signal rate that needs to be electrically multiplexed in the project is very high, the standard rate reaches 270Mbit/s, and it is not a homologous signal multiplexing, it is difficult and uneconomical to directly electrically multiplex the signal. It is necessary to first recover the clock of each signal, convert the high-speed serial signal into a low-speed parallel signal, and then adjust the clock pace of each signal through the FIFO chip circuit to achieve synchronization with the local clock, and then use the programmable chip to multiplex the two electrical signals to achieve time division multiplexing transmission. Only after this series of signal processing processes can a smooth demultiplexing process be achieved at the receiving end, which is also the main technical breakthrough point of this design.

In addition, locking of electrical multiplexing is also a problem. The more signal paths there are and the higher the rate, the more difficult it is to lock, and the higher the layout technology requirements for the PCB board. This problem can be well solved through the reasonable placement of various components and scientific filtering of clutter and other treatments.

Hardware Circuit

In this design, the most used is the latest powerful and stable digital video chipset launched by National Semiconductor. The decoding and serial/parallel conversion chip is CLC011; the encoding and parallel/serial conversion chip is CLC020; the clock recovery chip is LMH0046; the adaptive cable equalization chip is CLC014; the CPLD chip is LC4256V from LATTICE; and the FIFO chip is IDT72V2105 from IDT.

The processing process of the equalization circuit is shown in Figure 2. As shown in Figure 2, the single-ended input ASI/SDI serial signal is shaped after passing through the equalization circuit and converted into a set of differential signals, which is ready for the subsequent clock recovery process. After passing through the equalization circuit, the signal quality is greatly improved, and the input and output signal waveforms are compared as shown in Figure 3.

Figure 2 Circuit processing of the equalization part

Figure 3 Comparison of equalization circuit waveforms [page]

The processing of the clock recovery circuit is shown in Figure 4. As can be seen from Figure 4, the working mode of the chip is correctly set, a 27M clock is provided locally for the clock recovery chip to use, the equalized high-speed differential signal is input into the chip, and the clock signal in the serial signal is recovered after processing by the chip for use by the decoding circuit below. At the same time, the chip can also support the clock recovery function of high-definition signals.

Figure 4 Clock recovery circuit processing

The processing of the decoding circuit is shown in Figure 5. As can be seen from Figure 5, the serial clock and serial data recovered by the clock recovery chip are input to the decoding chip, and after serial/parallel conversion, 10-bit parallel data and 27M parallel clock are output for the clock adjustment of the following FIFO circuit. The timing diagram of the signal in each working mode is shown in Figure 6.

Figure 5 Decoding circuit processing

Figure 6 Signal timing diagram for each mode

The circuit processing of the FIFO is shown in Figure 7. The read clock uses the 27M parallel clock recovered by the encoding circuit, and the write clock uses the local 27M clock. The 10-bit parallel signal passing through the FIFO is synchronized with the local clock through adjustment, preparing for the subsequent input to the CPLD for electrical multiplexing. The electrical multiplexing part of the CPLD is as follows, where 2BP-S is the multiplexing program and 2BS-P is the demultiplexing program.

Figure 7 FIFO circuit processing process [page]

architecture SCHEMATIC of 2BP-S is

SIGNAL gnd : std_logic := '0';

SIGNAL vcc : std_logic := '1';

signal N_25 : std_logic;

signal N_12 : std_logic;

signal N_13 : std_logic;

signal N_15 : std_logic;

signal N_16 : std_logic;

signal N_17 : std_logic;

signal N_21 : std_logic;

signal N_22 : std_logic;

signal N_23 : std_logic;

signal N_24 : std_logic;

begin

I30: G_D Port Map (CLK=>N_25, D=>N_13, Q=>N_22);

I29: G_D Port Map (CLK=>N_25, D=>N_16, Q=>N_23);

I34 : G_OUTPUT Port Map ( I=>N_22, O=>Q0 );

I33 : G_OUTPUT Port Map ( I=>N_23, O=>Q1 );

I2 : G_INPUT Port Map ( I=>CLK, O=>N_25 );

I7 : G_INPUT Port Map ( I=>A, O=>N_12 );

I8 : G_INPUT Port Map ( I=>LD, O=>N_21 );

I6 : G_INPUT Port Map ( I=>B, O=>N_15 );

I12: G_2OR Port Map (A=>N_17, B=>N_24, Y=>N_16);

I16: G_2AND1 Port Map ( AN=>N_21, B=>N_22, Y=>N_24);

I21 : G_2AND Port Map ( A=>N_21, B=>N_12, Y=>N_13 );

I20: G_2AND Port Map (A=>N_21, B=>N_15, Y=>N_17);

end SCHEMATIC;

architecture SCHEMATIC of 2BS-P is

SIGNAL gnd : std_logic := '0';

SIGNAL vcc : std_logic := '1';

signal N_5 : std_logic;

signal N_1 : std_logic;

signal N_3 : std_logic;

signal N_4 : std_logic;

begin

I8 : G_OUTPUT Port Map ( I=>N_4, O=>Q0 );

I1 : G_OUTPUT Port Map ( I=>N_5, O=>Q1 );

I2 : G_INPUT Port Map ( I=>CLK, O=>N_3 );

I3 : G_INPUT Port Map ( I=>SIN, O=>N_1 );

I7: G_D Port Map (CLK=>N_3, D=>N_4, Q=>N_5);

I4: G_D Port Map (CLK=>N_3, D=>N_1, Q=>N_4);

end SCHEMATIC;[page]

The circuit processing process of the encoding part is shown in Figure 8. After the receiving optical module receives the data, the parallel data and synchronous clock are restored through the demultiplexing program of the CPLD, and then the original high-speed serial signal is restored through the encoding chip circuit. After being driven by the cable driver chip, it is finally output by the transmission device to complete the entire transmission process. Among them, the signal timing of the encoding circuit part is shown in Figure 9.

Figure 8 Encoding circuit processing

Figure 9 Coding circuit signal timing diagram

Conclusion

The design of the CPLD-based asynchronous ASI/SDI signal electrical multiplexing and optical transmission equipment uses the latest ASI/SDI signal electrical multiplexing/demultiplexing technology, which can realize time-division multiplexing transmission of two signals, replacing the previous multi-channel asynchronous signal transmission mode based on wavelength division multiplexing technology, greatly saving production costs and further improving the market competitiveness of the product.