FPGA Implementation of PSI Information Analysis Part of MPEG-2 Multiplexer

The multiplexer is a key device in the digital TV front-end platform. Its main function is to complete the multiplexing of the input multi-channel transport stream (TS). Its performance stability directly affects the operation of the front-end platform. Whether the multiplexer analyzes and processes the program special information (PSI) in the transport stream completely and comprehensively directly affects whether the operation results of other functional parts of the multiplexer are correct. The detection and analysis of PSI information is one of the first and most important parts in the multiplexer design. The following article will conduct an in-depth analysis and discussion on the PSI information detection problem.

1 TS stream syntax structure

The transport stream is based on TS packets, where each packet is 188 bytes long. These 188 bytes can be roughly divided into three main parts: packet header, adjustment field, and payload. The packet header occupies 4 bytes, as shown in Figure 1.

Synchronization byte: 8 bits, value 0x47, indicating the start of a TS packet. Transport error indication: 1 bit, when set to 1, indicates that there is at least one uncorrectable error in the relevant TS packet. Payload start indication: 1 bit, when with PSI information, set to 1 to indicate that the TS contains the first byte of the PSI part and has a pointer field field, otherwise it does not contain the first byte of the PSI. Transport priority: 1 bit, set to 1 to indicate that the relevant packet has a higher priority than other TS packets with the same PID but this bit is not set to 1. PID: 13 bits field, indicating the data type of the transport stream payload. Transport scrambling control: 2 bits, used to indicate the scrambling method of the TS packet payload. Adaptation field control: 2 bits, used to indicate whether the TS packet header is followed by an adjustment field. Continuity counter: 4 bits, increases with each transport stream packet with the same PID, and returns to 0 when it reaches the maximum value.

Program-specific information PSI is used to describe the composition structure of the TS stream. It includes the Program Association Table (PAT), Program Map Table (PMT), Network Information Table (NIT) and Conditional Access Table (CAT). PAT is the top layer of PSI information, which lists the PID values ​​of PMT corresponding to all programs in the transport stream. The corresponding PMT information and NIT information can be found according to the PID value of the program. The program map table PMT provides the mapping relationship between program numbers and the original streams that compose them. This mapping table is a collection of all program definitions in a TS stream. The network information table NIT is optional and its content is private, usually including the mapping of user-selected services and channel frequencies, satellite pulse transmitters, modulation characteristics, etc. The conditional access table CAT provides relevant information for the conditional access (CA) system, specifies the PID value of the EMM and related parameters.

2 PSI information extraction and analysis

Since the structures of the four tables of PSI information are not much different, the extraction algorithms are also roughly similar. Here, the PAT table is used as an example to introduce the extraction process of PSI information in detail. The analysis of TS stream is in bytes inside FPGA. The PAT syntax structure is shown in Figure 2.

PAT extraction process:

(1) First, find the TS packet in the transport stream whose PID 13 bits are all 0 and whose payload start indicator bit is 1.

(2) Then, the adaptive field control bit is used to determine whether the adjustment field is included, and the table_id is found in combination with the pointer_field field value. From this field to the CRC check byte, a CRC check is performed on all valid data.

(3) Next is the section_length field, from which the number of TS packets in the PAT segment can be obtained.

(4) The next two bytes are the transport stream identification field, and the next byte contains the version number information and whether the current segment is available. The current version number is retained and compared with the next version number to determine whether the version is updated. If the current segment is available, continue, otherwise return to (1).

(5) The next two bytes are the current segment number and the last segment number. From this information, we can know whether the information of all segments has been extracted, that is, whether a complete analysis of the entire PAT table has been performed.

(6) The cyclic field is processed once every 4 bytes. The program number in the first two bytes can be used to determine whether the PID in the last two bytes is PMTPID or NIT-PID. The CRC check is stopped immediately after the cyclic field ends and the check result is compared with the CRC four bytes in the bitstream to determine whether the transmission is wrong.

(7) At the end of the TS packet, determine whether the current PAT segment has ended. If not, continue to detect the next TS packet. If yes, further determine whether all segments have been analyzed. If all segments have been analyzed, give a signal indicating that all PAT analysis has ended. Otherwise, go to (1) and continue to analyze the next segment.

3 Hardware Implementation of Information Extraction

The information extraction block diagram is shown in Figure 3.

One TS stream first passes through the chip CY78933 for serial-to-parallel conversion and then enters the synchronization module for synchronization locking before other modules start working. As can be seen from Figure 3, the above detection modules work independently in parallel, but the PMT detection module, ELE detection module, NIT detection module and EMM detection module need to receive information provided by other modules in order to work effectively. Specifically, the PMT and NIT detection modules need to receive PID information provided by the PAT detection module, the ELE detection module needs to receive PID information provided by the PMT detection module, and the EMM detection module needs to receive PID information provided by the CAT detection module. [page]

3.1 Information extraction and synchronization module

According to the MPEG-2 standard, a valid TS packet is 188 B long, and its synchronization header is 8'h47. Only when the packet header is effectively identified can each bit of the data packet be analyzed strictly in accordance with the MPEG-2 standard. In the synchronization module detection, when 8'h47 is found, 8'h47 must be found every 188 B for 3 to 5 consecutive times (which can be set by parameters) to be considered to have achieved synchronization. In addition, considering that 16 B of forward error correction code can be added to the TS packet, the module is made 188/204 B adaptive, which can improve versatility.

3.2 Detection module

Since the hardware designs of detection modules such as PAT, CAT, PMT, and NIT are very similar, this article focuses on the hardware design of the PAT detection module, and the designs of other detection modules will not be repeated.

The PAT detection module works according to the PAT extraction process. If the PAT segment is found and the CRC check is correct, the PMT-PID and NIT-PID in it are extracted and sent to the PMT detection module and the NIT detection module respectively. After analyzing all the segments of the PAT table, the PMT, detection module and NIT detection module are started to perform real-time detection on the TS stream. If the PAT table is updated, the new information is sent to these two modules to ensure real-time tracking of the latest changes in the TS stream.

In terms of hardware implementation, from a practical point of view, considering the various situations that may occur in the actual bitstream, they are classified into three categories:

(1) A segment is carried by only one TS packet.

(2) A segment is carried by multiple TS packets.

For such a situation (i.e. the length of the segment is such that one TS packet cannot completely carry the segment), we need to consider where the first TS packet ends in the segment. This can be divided into three situations:

① The first TS packet ends in the interval from the table_id field to the last_sectiOn_number field of the segment. This is the case when most of the first TS packet is occupied by the adjustment field;

② The first TS packet ends at a byte in the loop field;

③ The first TS packet ends at a byte among the four CRC check bytes. Considering that there are more than three TS packets, it is more precise that the last TS packet only carries some of the CRC check bytes.

(3) One TS packet carries multiple segments

This type of situation is an extension of situation ③ in category (2). For example, a PAT table has two segments. After the first segment is carried by the first TS packet, only one CRC check byte is left, which needs to be carried by the second TS packet. Then it will be a great waste for the second TS packet to only carry this one CRC check byte. At this time, the second TS packet can be fully utilized. It can also carry the second segment, which is the case of one packet with multiple segments. For multiple situations such as a single packet, multiple packets in one segment (including three situations), and multiple segments in one packet, the design undoubtedly needs to give full play to the powerful advantages of the FPGA finite state machine to handle them.

The above situations are appropriately matched to the various states of the state machine. Logical judgment can be performed based on the information provided by the packet header and the table segment information, thereby controlling the transfer between various states. In code implementation, it is crucial to determine whether the control signal is accurate and timely after logical judgment. For example, the CRC check analysis of the PAT table is used as an independent module. When analyzing the table, the module must be accurately controlled. If the PAT has two TS packets, the module must be enabled in the table_id field of the first TS packet, and the module must be disabled at the end of the first TS packet. The CRC check module is enabled again at the fifth byte of the second PAT packet, and the module is turned off before the CRC check byte. In short, the control signal must ensure that the CRC check module checks all valid information in the PSI table.

It should also be noted that the PMT detection module does not need to consider multiple segments in its implementation, but there are two descriptors that need to detect CA descriptors; the NIT detection module can detect specified descriptors, such as satellite transmission system descriptors, etc.; the ELE detection module detects elementary_PID, PCR PID and possible ECM_PID. If this module can work properly, it means that the PMT detection module works correctly; similarly, if the EMM detection module can work properly, it means that the CAT detection module works correctly.

3.3 Resource Optimization

As shown in Figure 3, PAT detection and CAT detection are the same module. This is also an innovation in the hardware implementation of this article. The reason for this is that the author cleverly integrated the detection and analysis of CAT into the detection and analysis of PAT in the writing of program code, and the resources consumed by the integrated detection module are only slightly more than the resources consumed by the original PAT detection module, which means that the detection of CAT is completed with almost no increase in hardware resource consumption, thus greatly saving the valuable logic resources inside the FPGA.

After careful analysis and comparison, the author found that the PAT table and the CAT table have amazing similarities, which greatly facilitates the writing of hardware language. The difference between PAT and CAT is mainly in the loop field, and the number of bytes in other fields can correspond well. If the processing of the loop fields of the two tables is separated into two small modules, the remaining part can well integrate the processing of PAT and CAT. The integrated module only needs to give appropriate control to these two small modules.

4 Actual Test

This design uses the hardware platform DE2 development board, FPGA model EP2C35F672C6N, and the interface chip is connected to the FPGA through the DE2 board GPIO interface. The test code stream includes real-time code stream converted from satellite signals and artificial non-real-time code stream. For Class A, the real-time code stream converted from the Asia-Pacific satellite frequency 4095H is used for testing, as shown in Figure 4, from left to right: the digital tube values ​​1 and 3 respectively indicate that there is a set of programs, which has 3 PIDs, namely 13′h0021, 13′h00A0, and 13′h0050; three red LED lights are on to indicate that PAT, PMT and basic audio and video packages are found, and two green LED lights are on to indicate that the reception synchronization and extraction and analysis of PSI information are completed. The number of programs and PID values ​​displayed by the DE2 board are the same as those displayed by a professional digital satellite receiver, indicating that the PSI information detection is correct. For other possible situations, since they are rarely seen in actual code streams, artificially constructed code streams that meet the standards are used for verification, and the results are also correct.

5 Conclusion

With the expansion of the application scope of multiplexers in the future and the increase in data traffic, there will be multiple packets in one segment or multiple segments in one packet in the actual bit stream. This article provides practical designs for various situations that may occur in the actual bit stream, which can fully ensure that the multiplexer can perform complete and comprehensive PSI information detection no matter how large the traffic volume is, and has strong practical significance.