Study on active area shape distortion in advanced DRAM processes

Microstructural inhomogeneities (loading effects) and their impact on device performance: a study of active area shape distortion in advanced DRAM processes

In DRAM structures, the charging and discharging of capacitor storage cells is directly controlled by transistors. As transistor size shrinks to the physical limit, manufacturing variations and micro-loading effects are becoming the main factors limiting DRAM performance (and yield). For advanced DRAMs, the size and shape of the transistor's active area (AA) are important factors affecting yield and performance. In this study, we will show you how to use SEMulator3D to study the AA shape distortion and the associated micro-loading effects and manufacturing variations in advanced DRAM processes.

AA distortion and its mechanism

Almost all commercialized DRAM products from leading DRAM manufacturers have AA shape distortion. In addition to centerline instability, this distortion is also reflected in critical dimension differences around the cutting area (see Figure 1).

Figure 1. AA cross-section of 1x DRAM devices from three different manufacturers.

Figure 2 is a simplified schematic diagram of the transistor fin etching process. In the fin (AA) dry etching process, the sidewall will have a tapered profile due to the passivation effect of the etching byproducts. Since the area where point A is located needs to remove more silicon than the area where point B is located, area A consumes more reactants and produces more byproducts (see Figure 2 (b)). In this way, after the fin is etched, the passivation taper of the sidewall of area A will exceed that of the sidewall of area B (see Figure 2 (c)), which is why the AA shape is distorted.

Figure 2. AA shape distortion in fin etching process (a) Top view of hard mask before etching; (b) Comparison of pattern etching between A and B areas; (c) Top view after fin etching

Modeling AA distortion

SEMulator3D uses an innovative pseudo-3D approach to achieve graphical modeling based on 2D approximation functions. With this modeling technique, we can create a 3D model of a DRAM device and simulate the AA shape distortion phenomenon. Figure 3 shows the DRAM 3D structure and plan view, layout design, and graphic-related masks simulated by SEMulator3D. By comparison, it can be seen that the AA distortion morphology presented in Figure 3 (d) and Figure 1 (c) is similar, which proves that the model can correctly reflect the actual manufacturing results. Figure 4 shows the AA cross-section of different fin heights, from which it can be seen that the distortion at the bottom of the structure is much higher than the distortion at the top of the device.

Figure 3. (a) Layout design; (b) PDE mask generated by hard mask; (c) 3D structure after fin etching; (d) AA shape from the plane cut in the middle of the fin

Figure 4. AA cross-section of different fin heights (a) 3D view cut along the word line; (b) cross-sectional view cut along the word line; (c) 3D view cut along the top of the fin; (d) 3D view cut along the middle of the fin; (e) 3D view cut along the bottom of the fin

Device simulation and analysis

In a DRAM cell with buried word lines, the transistor channel is located near the middle of the fin, where the shape distortion is more severe than at the top of the fin (see Figure 4 (c) and (d)). In this case, the fin CD under the channel is also much larger due to the sidewall passivation.

Figure 5. DRAM structure after capacitor contact formation (a) 3D view; (b) cut-out single device; (c) fin cross-section and port definition

To evaluate the impact of AA shape distortion on device performance, we used SEMulator3D to model sidewall crack angles of 0.1, 2.5, and 5 degrees to simulate different degrees of AA distortion, and performed electrical analysis using a single device from a full-loop DRAM structure (see Figure 5 (b)). Electrical measurements can be obtained by assigning electrical ports (source, drain, gate, and substrate) through SEMulator3D (see Figure 5 (c)), and then the built-in drift/diffusion solver of SEMulator3D can be used to calculate the changes in electrical performance that may be caused by different degrees of AA distortion.

Figure 6 shows the off-state leakage current distribution of the fin at different sidewall angles. It can be seen that regardless of the sidewall angle, most of the leakage current is concentrated in the center of the fin, which is far away from the gate metal and has little effect on the gate electric field. Since the gate controllability of thick fins (larger sidewall angles) is lower, their leakage current density is much higher than that of thinner fins.

Figure 6. Channel leakage morphology from the fin surface to the center at different sidewall angles

Summarize

This study used SEMulator3D to model and analyze the transistor micro-loading effect in advanced DRAM processes. The analysis results show that the micro-loading effect in pattern-related etching will cause AA shape distortion, which will seriously affect the electrical performance of the device. The off-state leakage involved is a key factor in determining the data retention capability of DRAM cells.