Cadence Protium S1 FPGA-based prototyping platform

The IoT spans multiple application areas, and the requirements of design teams can vary greatly depending on the end application area. Power, performance, and cost are priorities in chip design, while application areas such as automotive and aerospace/defense also require functional safety, and in other areas, information security is critical or field upgradability is a requirement.

Verification, prototyping, and software development are commonalities among these areas and design requirements. To allow embedded software development to proceed, early verification techniques were often considered too slow, while abstractions using virtual platforms such as QEMU were sometimes not accurate enough.

FPGA-based prototyping has long been the platform of choice for pre-silicon software development. Hardware emulation in tools like the Cadence Palladium Z1 Enterprise Emulation Platform can scale execution performance from MHz to 100s of MHz at a lower cost, putting it in the hands of more developers on software teams.

Traditionally, the barrier to FPGA-based prototyping has been the bring-up process, which can sometimes take months before it is available to software developers. The reason for this is the need to remap the ASIC design from its actual silicon into the structure provided by the FPGA, which requires remapping various parts of the design.

Prototype Verification Process

For starters, the memory in the ASIC needs to be mapped to available resources in the FPGA or to a daughter card that has specific additional memory (e.g. DDR). Dealing with clocking the ASIC can be a nightmare, with more than 10 clocks to synchronize in more complex designs on the PCB and FPGA. Partitioning a design across multiple FPGAs is not an easy task and often requires multiplexing multiple signals on the same pin using low voltage differential signaling (LVDS) technology.

Traditionally, larger companies have had prototyping teams that take the RTL versions that the design team is developing and map them into the FPGA. However, as the complexity of designs increases, it becomes increasingly difficult to perform all of the above tasks.

With the Protium S1 FPGA-based prototyping platform, Cadence has redeveloped the prototyping flow and focused on reducing prototyping time from months to weeks or even days by achieving consistency between Palladium Z1 simulation and Protium S1 FPGA-based prototypes, and reusing some of the front-end simulation for prototyping.

Complex manual memory modeling is automated using memory models known from simulation; the compilation flow takes care of partitioning and clock synchronization between FPGAs. Netlists to be mapped into the FPGA fabric can be verified in simulation, saving valuable placement and routing time. Bugs are found approximately 5 times faster in FPGA-based prototypes than in simulation, thus facilitating better debugging capabilities in simulation.