TSMC's 2nm process breakthrough, how can it extend the life of "Moore's Law"?

This year, due to the US ban on Huawei and SMIC, TSMC, a chip manufacturing company that was originally at the back end of the chip industry, has been brought into the spotlight again and again, and has been scrutinized by the outside world inside and out.

At this time, TSMC is ushering in the highlight of its development. Although TSMC lost Huawei's large orders after the Huawei ban came into effect in September, the vacant production capacity was immediately divided up by companies such as Apple and Qualcomm, and is in full production. Combined with factors such as the growth of electronic consumer products under the epidemic, TSMC will usher in a growth rate that is 10% higher than the global wafer foundry industry growth rate this year.

In particular, TSMC's 5nm7nm process, which is ahead of other foundries, accounts for more than 43% of revenue, and its revenue capacity is comparable to a "money printing machine." At the same time, TSMC has spared no effort in the research and development of more advanced processes and equipment investment.

In response to the demand for expanded production capacity of new process technologies, TSMC has ordered 13 new extreme ultraviolet (EUV) lithography machines from ASML, requiring all to be delivered in 2021. It is estimated that 13 sets of EUV may cost TSMC up to US$2.284 billion. At the same time, TSMC has just decided to increase salaries by 20% starting next year, on the one hand to motivate employees, on the other hand to attract talents and avoid being poached by other competitors with high salaries, using real money to retain engineers who are willing to continue to work hard to build chips.

Amid a prosperous business outlook, TSMC also maintains its lead in the technology layout of more advanced processes. According to Taiwanese media reports, TSMC has recently made a major breakthrough in the 2nm process, and its R&D progress has exceeded expectations. It is expected that the yield rate of risk trial production will reach 90% in the second half of 2023.

Instead of focusing on the current excitement, we might as well follow this technical clue and look at TSMC’s experience in maintaining advanced process technology and how it is trying to “extend the life” of Moore’s Law, which is on the verge of failure.

2nm has been broken through, 1nm is no problem

Let’s first look at TSMC’s breakthrough in process technology from a technical perspective.

TSMC's breakthrough in 2nm process technology comes from the adoption of a new GAA transistor architecture. Different from the fin field effect transistor (FinFET) architecture used in 3nm and 5nm processes, this time 2nm uses a new multi-bridge channel field effect transistor (MBCFET) architecture, which is based on the gate-all-around (GAA) process and can solve the physical limit problems such as current control leakage caused by process miniaturization of FinFETch.

It can be said that the emergence of GAA process technology is equivalent to extending the life of Moore's Law for about another five years. Moore's Law states that every 18 to 24 months, the number of components that can be accommodated on an integrated circuit will double, and the performance of the chip will double accordingly.

We know that this law is not a theorem that will definitely happen, but only a prediction. This prediction is based on the premise that the semiconductor process technology can be steadily improved. However, the semiconductor industry now relies on the FinFET architecture and has achieved mass production of 7nm and 5nm process chips. The latest iPhone12 and Huawei Mate40 that many people have bought use 5nm process chips.

However, as the transistor scale moves towards 5nm or even 3nm, the size of FinFET itself has been reduced to the limit, whether it is the fin distance, short channel effect, leakage or material limitations, making transistor manufacturing difficult to complete.

Now, relying on FinFET technology, TSMC's chip process has reached the end of 3nm, and it will encounter bottlenecks if it goes down. According to reports, GAA technology is a transistor based on all-purpose gate FinFET technology developed by the Institute of Science and Technology and the National Nanowafer Center in 2006, and Samsung is taking the lead in using the MBCFET architecture developed based on GAA technology in the 3nm process. For robustness reasons, TSMC chose to continue using FinFET technology in the first generation 3nm process, and adopted the same MBCFET architecture as Samsung in the 2nm process.

TSMC's progress in the new process will increase the speed and performance of the new generation of chips by 30% to 40%, and reduce power consumption by 20%-30%. Correspondingly, the research and development cost of the new process will be as high as US$500 million, which is indeed a straight increase compared to the US$60 million cost of the 28nm process.

Now, TSMC has relied on its accumulation of EUV micro-development technology and key nanosheet stacking technologies to improve the development yield of the 2nm process beyond expectations.

According to TSMC's official statement at the recently held "2020 World Semiconductor Conference", chip manufacturing technology will continue to advance, and Moore's Law will continue to apply at 3nm, 2nm, and 1nm. According to the information currently disclosed, the production layout of 2nm chips will be built and developed in Hsinchu, Taiwan.

Multi-pronged approach to lay out a complete technology map for leading processes

From the above technical introduction, we can see that TSMC's 2nm process adopts the GAA process architecture, although it is not developed by itself. In the 3nm process, it has not adopted the MBCFET architecture as aggressively as Samsung. However, if we want to give full play to the advantages of the GAA architecture, we must see TSMC's technical advantages and accumulation in maintaining process leadership and production yield.

For example, taking the 3nm process as an example, TSMC continues to use the FinFET architecture transistor design. On the one hand, it is precisely because its R&D team has brought the performance of FinFET to a new level. Compared with 5nm, 3nm has a 10-15% increase in speed, a 25-30% reduction in power consumption, and a 1.7-fold increase in logic density. SRAM density will also increase by 20%. On the other hand, 3nm can be mass-produced in the second half of 2022, which will enable customers who place orders to achieve rapid technology upgrades and be the first to launch leading products.

From TSMC’s technological layout, we can identify the factors for its success in process technology.

First, its long-term investment has gained leading technology research and development advantages. For example, in order to meet the yield of the new process technology, TSMC has successfully produced 32 Mb nano-sheet SRAM on the Nano-Sheet structure, which has obvious advantages in low voltage and power consumption; in 2D materials, TSMC has obtained very high On-current performance based on 2D sulfide materials including molybdenum sulfide and tungsten sulfide; in power management, TSMC researchers use carbon nanotubes embedded in a CMOS design to replace the current control function of Power Gating, providing new ideas for further miniaturization in the future.

The second is the long-term technology cooperation industry chain formed by TSMC. ASML, as an early lithography supplier that established cooperation with TSMC, not only provides equipment to TSMC, but also receives technical feedback from TSMC. Currently, TSMC has invested in multiple aspects of EUV lithography technology, such as OPC, masks and photoresists. For example, TSMC has achieved the industry's smallest 18nm mental pitch by using self-aligned pads in combination with EUV technology, which is of great help to transistor miniaturization.

Then there is the optimization and transformation of the process flow. In order to cope with the crisis of Moore's Law approaching failure, the perspective of miniaturizing transistors and increasing density to improve chip performance is failing. TSMC has promoted a number of front-end and back-end 3D packaging technologies to improve chip performance. For example, SOIC 3D stacking technology is implemented in the front end of chip manufacturing, and CoWoS and InFo 3D packaging technology is implemented in the back end. These technologies help to achieve transistor miniaturization while further improving the yield.

In addition, a very important point is TSMC's long-term accumulation in special processes. This may be a point that is rarely noticed. TSMC has extensive production line investment in MEMS, image sensors, embedded NVM, RF, analog, high voltage and BCD power IC. At the same time, it also adds advanced ULL&SRAM, RF&Analog and eNVM technologies on the basis of logic IC technology to achieve low power consumption and improve analog technology. Special processes will promote the development of IoT scenarios and AI scenario equipment.

The above series of technical advantages are due to TSMC's huge R&D investment. According to data, in recent years, TSMC's annual R&D investment has reached 10 billion US dollars. TSMC's leading layout in technology routes and long-term huge R&D investment are actually related to the foundry factory innovation model it created, and also to TSMC's own geographical location and industrial opportunity period.

Focused investment and independent research and development: TSMC's technology leadership

We see that TSMC's steady advancement in the 3nm process's architecture route and leading mass production, as well as the upgrade and smooth progress of its architecture route in the 2nm process, all stem from its long-term R&D investment and technological accumulation in the entire semiconductor wafer manufacturing.

This gives us an illusion that completing these actions can achieve dominance in the semiconductor industry and continue the legend of Moore's Law. But in fact, this is related to the unique innovation model established by TSMC at the beginning of its establishment, and also to the correct choices made by TSMC at several key technical intersections.