A Design of Reconfigurable DSP System Based on NiosⅡ

　　Nios II Embedded System Design Flow

　　The NiosII embedded processor is optimized for single-chip programmable system design. It is a user-oriented, flexibly customizable general-purpose RISC (reduced instruction set) embedded CPU. It uses the Avalon bus structure communication interface, with enhanced memory, debugging and software functions, and can be developed using assembly or C, C++, etc. for program optimization. NiosII has a 32-bit instruction set, 32-bit data channel, and configurable instruction and data buffers. Different from the characteristics of ordinary embedded CPU systems, its peripherals can be flexibly selected or added or deleted, and user logic can be customized as peripherals, allowing users to customize their own instruction sets. Customized instructions composed of hardware modules can complete complex software processing tasks through hardware algorithm operations, and can also access memory or interface logic outside the NiosII system. Designers can use NiosII and external Flash, SRAM, etc. to form an embedded processor system on FPGA.

　　A complete SOPC system based on NiosII is a complex system of hardware and software, so it can be divided into hardware and software during design. The hardware design of NiosII is to customize the appropriate CPU and peripherals, which is completed in SOPC  Buider and QuartusII. Here, many features and even instructions of NiosII CPU can be flexibly customized. A large number of IP cores provided by Altera can be used to speed up the development of NiosII peripherals and improve peripheral performance. You can also use third-party IP cores or VHDL to customize peripherals yourself. After completing the hardware development of NiosII, SOPC  Buider can automatically generate a software development kit SDK corresponding to the customized NiosII CPU and peripheral system, memory, peripheral address mapping, etc., and enter the software development process based on the generated SDK. Users can use assembly or C, or even C++ to design embedded programs, and use GNU tools or other third-party tools to compile, connect and debug programs.

　　Single-chip DSP system architecture

　　This system is a single-chip DSP reconfigurable system that can complete the operation of various functions in digital signal processing. The NiosII software processor mainly completes human-computer interaction and control functions; the logic module of the FPGA completes the corresponding hardware functions after receiving control signals and data from the NiosII processor. The system block diagram is shown in Figure 1. In addition to the soft-core processor NiosII, the memory, I/O interface, and application modules such as FIR digital filter, IIR digital filter, DDS, etc. can all be embedded in the FPGA as peripherals. In this way, the digital signal processing part of the entire DSP is fully integrated in the FPGA device, and each module is controlled by the NiosII processor. There is an Avalon bus in the NiosII processor system, which specifies the port connection between the controller and the slave module and the timing of the communication between the modules. The digital frequency synthesizer (DDS) is connected to the Nios II processor through the Avalon bus, which can easily complete the control and data transmission.

　　In this system, the FPGA uses Cyclone EPIC12, which has 12060 logic units (LE) and 2 phase-locked loops (PLL), provides 6 outputs and hierarchical clock structures and complex clock management circuits. Under the control of the NiosII processor, the entire system can realize FIR, IIR digital filtering, fast Fourier transform (FFT) algorithm, encoding/decoding and other functions. The system can also design DDS functional modules and form a signal generator with digital control frequency modulation, orthogonal carrier modulation and demodulation, digital control phase modulation and other functions. The selection of each functional module in the system and the selection of output signal modulation mode and frequency can be freely selected through external buttons.

　　System hardware design

　　The hardware system of the system includes three parts: FPGA, memory and peripheral components. The FPGA part needs to be designed in SOPC Buider, including NiosII CPU core, internal clock, Avalon bus controller, JTAG_UART communication module connected to NiosII core for downloading and debugging programs, DDS interface module and DDS module, FIR, IIR digital filter interface module and function module, encoding/decoding module and interface module, flash memory module, etc. Each peripheral module core is connected to NiosII through the on-chip Avalon bus. In order to make the NiosII system with DSP processor function work normally, some control keys are connected to the periphery of FPGA to schedule the application of each module.

　　Building a Nios II Embedded Processor System

　　First, use QuartusII to establish a project, select the target device as Cyclone EPIC12, use SOPC Builder to create NiosII component model, generate hardware description file, lock the pins, perform synthesis and adaptation, and generate NiosII hardware system download file. Then establish NiosII embedded system, add various components required from SOPC Builder component column: such as NiosIICPU Core, timer Timer, JTAG_UART, Avalon tri-state bus bridge, key input I/O port, Flash, etc. In addition, in order to realize the read and write access of NiosII processor to EPCS Flash memory, an EPCS Serial Flash Controller component is also added. Through this controller, the SOF file used for FPGA configuration and the software running by CPU are stored in the EPCS device together, so as to greatly simplify the hardware system composition structure. In order to ensure the legality of the address arrangement of all components, the addresses of each component should be automatically allocated, and finally the whole process is compiled, that is, analysis, synthesis, adaptation and output file assembly are performed to complete the design of NiosII hardware system.

　　After the NiosII hardware system design is completed, the configuration file is downloaded to the specified FPGA. Through the SOPC Builder software window, you can enter the NiosII DSK software development environment for software design.

　　Establishment of DSP processor function system

　　Using DSP Builder to design DSP modules on FPGA can achieve high-speed DSP processing. However, in practical applications, since DSP processing algorithms are often complex, if DSP Builder is used alone to implement pure hardware DSP modules, it will consume too many hardware resources and sometimes fail to complete complex operations. Some operations that appear repeatedly in DSP algorithms, such as complex multiplication, integer multiplication, floating-point multiplication, etc., do not have special related instructions in general CPUs. Using the custom instruction feature of Nios II, in system design, MATLAB, DSP Builder or VHDL can be used to design and generate hardware modules such as complex multipliers, integer multipliers, floating-point multipliers, etc. After making some modifications to the above files in the QuartusII environment, they can be customized as corresponding instructions in the SOPC Builder window, and the clock cycle for executing the instruction can be set or modified. When performing DSP algorithm operations, these custom instructions can be used for embedded programming through assembly or C, or even C++.

　　The complex multiplier model designed with MATLAB and DSP Builder is shown in Figure 2. It completes 16-bit complex multiplication. The bit width of the imaginary part and the real part are both 16 bits, and a 32-bit value can be used to represent the complex number. In the design, NiosII is 32-bit data, which can just hold 2 complex numbers.

　　To set this complex multiplier hardware module to the corresponding instruction, you need to do the following: click the SignalCompiler icon to convert it, select the device (use Cyclone), select the QuartusII synthesizer, and generate the PTF file of SOPC Buider after conversion. After exiting MATLAB, modify the top-level VHDL file of the complex multiplier generated after conversion in the QuartusII environment. Double-click the cpu item in the SOPC Buider window to enter the instruction addition editing window; click the Import button to enter the module file addition window; click the Add button to open the top-level file; click the Read port-list from files button to get the port addition status display window; click the Add to System button to add the complex multiplier design module and set this hardware module to the custom complex multiplication instruction comp. You can also modify the instruction cycle of the instruction. Click the Generate button to generate SOPC.

　　In addition, the peripherals of NiosII can be customized arbitrarily. All the peripherals of NiosII system are connected to NiosII CPU through Avalon bus. Avalon bus is an on-chip bus with a relatively simple protocol. NiosII exchanges data with the outside world through Avalon bus. In this system, the Avalon Slave peripheral method is used to add the customized Avalon bus component A/D conversion interface module and D/A interface module to control the operation of the sampling ADC and the waveform data output of the high-speed DAC. The customized Avalon bus component DDS module interface and DSP function conversion control interface are used for NiosII CPU to control the DDS module and to control the selection of DSP functions through an external keyboard.

　　System software design

　　After the instructions are generated and the bus and various peripheral components that need to be added (such as various interfaces, flash, etc.) are added, the SOPC system based on NiosII is compiled and downloaded to the FPGA. While the NiosII hardware system is generated, SOPC Buider helps users generate the corresponding SDK (software development kit). Since the system composed of Nios CPU and its peripherals in hardware development is customized, the mapping of memory and peripheral addresses are different, and a proprietary SDK is required. The user's newly customized instructions must also modify the original compilation tool, which is automatically generated by SOPC Buider.

　　After the SDK is generated, you can start the system software design. Here, the software development and design is similar to the development and design of the usual embedded system. The only difference is that the embedded system you face is customized and tailored, so it will be less limited by the hardware. You can use assembly, C, and C++ to design embedded programs, and use GNU tools or other third-party tools to compile, connect, and debug programs.

　　For example, after setting the complex multiplier hardware module to the corresponding instructions, lock the pins and compile the whole process. Then use QuartusII to edit the C program for testing. Run the C program in the Nios CPU in the FPGA. After the test is successful, the complex multiplication instructions can be used when encountering complex multiplication in DSP calculations.

　　The DDS module is still embedded in the FPGA in the form of hardware, and the amplitude, phase and frequency modulators can be designed using DDS as needed.

　　Conclusion

　　This design method of generating instructions from commonly used hardware modules and coexisting software and hardware can realize more complex DSP operations in FPGA. The entire system, except for ADC, DAC and control selection keyboard, can be realized in one FPGA programmable chip. Various interface module components can also be customized through the Avalon bus to improve the flexibility of the entire DSP system and combine the flexibility of software with the high speed of hardware.