A brief analysis of the basic structure of DSP chips

　　In order to quickly realize digital signal processing operations, DSP chips generally use special software and hardware structures. The following briefly introduces the basic structure of DSP chips.

　　(1) Harvard Structure

　　The main feature is that the program and data are stored in different storage spaces, that is, the program memory and data memory are two independent memories, each memory is independently addressed and accessed. Corresponding to the two memories, the system is equipped with a program bus and a data bus, which doubles the data throughput. Since the program and data are in two separate spaces, instruction fetching and execution can be completely overlapped.

　　(2) Pipeline operation

　　Pipeline is related to Harvard architecture. DSP chips widely use pipeline to reduce instruction execution time, thereby enhancing the processing power of the processor. The processor can process two to four instructions in parallel, each instruction is in a different stage of the pipeline. The following is an example of a three-stage pipeline operation:

　　CLLOUT1

　　Fetch NN-1N-2;

　　Decode N-1NN-2;

　　Execute N-2N-1N,

　　(3) Dedicated hardware multiplier

　　Dedicated hardware multiplier, the faster the multiplication speed, the higher the performance of the DSP processor. With a dedicated application multiplier, multiplication can be completed in one instruction cycle.

　　(4) Special DSP instructions

　　DSP uses special instructions.

　　(5) Fast instruction cycle

　　Special DSP instructions: DSP chips use special instructions. Fast instruction cycle, Harvard structure, pipeline operation, dedicated hardware multiplier, special DSP instructions, plus the optimized design of integrated circuits can make the instruction cycle of DSP chips below 200ns.