PCI2040 bridges TMS320VC5420 to PCI bus

　　PCI2040 is a bridge chip produced by TI specifically for use between DSP and PCI bus. The internal schematic diagram is shown in Figure 1. For a detailed introduction to PCI2040, please refer to the relevant information from TI (see Reference 1). The PCI local bus standard was proposed by Intel Corporation and formulated by the Peripheral Components Special Interest Group (PCISIG). At present, the PCI bus is no longer a local bus, but has become a popular high-end bus and modern bus, which is widely used in graphics, images, animations and other various peripherals to transmit high-speed data.

　　The main advantages of the PCI bus are high performance (data transmission rate can reach 132/264Mbps), strong bus versatility, low cost, easy and flexible use. PCI2040 can interface with the 8-bit TMS320c54xHPI bus or the 16-bit TMS320c6x HPI bus. This article describes how to connect the 16-bit HPI interface of TMS320VC5420 to the PCI bus through the 16-bit C6X mode interface of PCI2040.

　　1 Two ways to map TMS320VC5420 to main memory

　　TMS320VC5420 is a DSP with two cores A and B. Depending on the number of TMS320VC5420, there are two ways to map TMS320VC5420 to main memory or PC storage space. If the number of TMS320VC5420 is less than three, mapping mode 1 can be used (Figure 2). If the number of TMS320VC5420 is more than two, mapping method 2 (Figure 3) can be used. This method maps each DSP to a specific memory space, and each DSP core or DSP subsystem occupies the same storage space. It is worth noting that the offset of the control space is relative to the value represented by the control space base address register at 14H in the 256-byte PCI configuration register on the PCI2040.

　　2 Hardware considerations

　　The TMS320VC5420 is a dual-CPU device with two independent C54X subsystems capable of core-to-core communication. Although PCI2040 is not specifically designed to interface with dual-CPU devices, the interface can still be implemented after special processing. There are three main aspects that need to be considered: ① Conversion from C6201HPI protocol to TMS320VC5420 HPI-16 protocol; ② Switching between two DSP cores; ③ Handling of multiple resets and multiple breaks.

　　2.1 Conversion of C6x HPI protocol to TMS320VC5420 HPI-16

　　TMS320VC5420 provides two operating modes for the HPI bus. In non-multiplexed mode (HMODE=1), the TMS320VC5420 HPI interface provides an 18-bit address bus for accessing all internal memories. Multiplexing mode (HMODE=0), address and data multiplex the same pin.

　　The PCI2040 only completes multiplexing mode, so the HMODE pin of the TMS320VC5420 must be dragged to the address. In addition, since the HPDY signal of C6X HPI is active at low level, and the HRDY signal of TMS320VC5420 is active at high level, a converter (such as SN74ALCV04) must be used for TMS320BVC5420 so that the VCC_H terminal can be directly connected to the VCC terminal.

　　2.2 Switching between two DSP cores

　　Select the accessed DSP subsystem through the SELA/B pin of TMS320VC5420. For example, you can connect the PCI2040 pin GPIO2 to SELA/B, so that you can select core A or core B through the high and low levels of GPIO2.

　　2.3 Multiple HRST TMS320BVC5420 has two ways to control the reset function of each subsystem.

　　The first one is to keep the A_RS and B_RS pins low when the HPIRS pin transitions from low level to high level, so that the application code can be downloaded to the DSP while the two cores are in reset state. After downloading, you can reset A_RS and B_RS to high level and drag the two subsystems out of reset state. Keeping the A_RS and B_RS pins high while the HPIRS pin transitions from low to high can also download application code to the DSP while both cores are in reset. After downloading, the subsystem can be dragged out of the reset state by writing to address 2FH. In addition, specific subsystems can be selected based on the value of SELA/B.

　　Second, use Power-on reset logic to reset each subsystem (A_RS and B_RS). In this case, you need to connect the HPIRS pin to the HRST pin of PIC2040. Note that after the application download is complete, there must be a write operation to address 2FH to drag the subsystem out of reset.

　　2.4 Handling two HINT interrupts generated by the same DSP

　　How multiple interrupts are handled can be determined based on the number of TMS320VC5420 connected to PCI2040. If there are two or less TMS320VC5420, you can connect A_HINT of the first TMS320VC5420 to HINT0 and B) HINT to HINT1. Connect HINT2 and HINT3 of PCI2040 to A_HINT and B_HINT of the second TMS320VC5420 (as shown in Figure 4). In this case, the memory setting uses mapping mode 1. If the board contains multiple TMS320VC5420s, the two interrupts on each DSP need to be ANDed (as shown in Figure 5). The interrupts on each DSP share the same interrupt line of PCI2040, so it is impossible to know the interrupt requested by the subsystem on a certain DSP. At this time, 1 must be written to the HINT bit of the HPLC register in each subsystem.

　　In this case, the memory configuration uses mapping mode 2.

　　3 Software considerations

　　C6X has a 16-bit HPI interface that uses a 32-bit word length, so all HPI operations require two HPI cycles. Since the 16-bit interface of PCI2040 is used to interface with C6X, PCI2040 also requires two HPI cycles. Unlike C6X, TMS320VC5420 uses a 16-bit word length, so that only one HPI cycle is needed to complete an operation. Therefore, when programmers access TMS320VC5420 through PCI2040, they must know that reading and writing to DSP need to follow special principles.

　　3.1 Write data to HPIA, HPIC and HPIC registers

　　When writing data to HPIA (HPI address register), HPIC (HPI control register) and HPID (HPI data register), since the two cycles of PCI2040 operations on the HPI port are for the same register, the data written in the first cycle will be overwritten in the second cycle. Therefore, the data should be written to the register multiple times to ensure the correctness of the written data (Figure 6).

　　3.2 Read data from HPIA, HPIC, HPID registers

　　When reading data from the HPIA, HPIC, and HPID registers, PCI reads these registers twice and returns the upper and lower parts of the PCI double byte (Figure 7).

　　3.3 Utilize the automatic increment feature. In order to maximize the performance of HPI, when reading and writing the HPID register, use the automatic increment feature of the HPIA in the first and second HPI cycles of the DSP register. The auto-increment feature allows two words to be read and written continuously via the PCI bus, ultimately enabling a 32-bit word length to be read and written at one time, thus effectively accelerating the data transfer rate.