Interrupt technology and its implementation of TMS320F206

　　Informatization, symbolized by the information highway, has become a major trend in social development and is gradually becoming a reality. Informatization is based on digitalization, and digital signal processing technology is one of the most important basic technologies of digitalization. In the past ten years or so, the performance of various integrated single-chip digital signal processors (DSPs) has been greatly improved. There are more and more software development tools and they are getting better and better; while the price has The price has dropped significantly, making digital signal processing devices and technologies easier to use, and the price acceptable to the majority of users. Judging from the various DSP products on the market, Texas Instruments products account for half of them, especially the TMS320 series. The TMS320F206 discussed in this article is the fixed-point digital signal processing chip in this series.

　　1 Structural features of TMS320F206

　　TI's TMS320F206 chip is manufactured using a static CMOS integrated circuit process. The structural design is based on the TMS320C20X chip and only requires a low voltage of 5V to operate. Its advanced Harvard architecture, on-chip peripherals, on-chip memory and rich command set greatly improve its speed and reliability.

　　The main features of TMS320F206 are: (1) 32K%26;#215;16-word FLASH EEPROM greatly reduces development costs; (2) Adopts 100-line TQFP packaging technology; (3) 64K-word program storage space, 64K The data storage space of words and the I/O space of 64K words operate independently through three parallel buses (PBA, DRAB, and DWAB). Therefore, the program space and data space can be accessed at the same time. In a specified machine cycle, the central arithmetic logic unit can perform up to three parallel memory operations; (4) The 4.5K RAM on-chip enables the chip to achieve fast DSP calculations, and Enables most operations to be completed within one instruction cycle; (5) Rich instruction set and flexible addressing mode; (6) There are four pipeline operations and nine levels of interrupts, and most interrupts can be shielded by users and can be Flexible control via software.

　　2 TMS320F206 can be broken

　　In the program space of TMS320F206, the interruptable vector occupies the position 00~3fh, and the priority of the interrupt is also fixed. Therefore, when developing programming, you must first compile an interrupt vector table, and you should also program unused interrupts. , and let it return to an empty position to avoid unexpected situations. The interrupts of TMS320F206 have many special features. For example, HOLD and INT1 share an interrupt vector, and INT2 and INT3 also share an interrupt vector. If a lot of interrupts are used in actual applications, it is difficult to control interrupts. At this time, it is necessary to use its three interrupt registers flexibly. These three registers are introduced below. (1) The 16-bit interrupt flag register (IFR), whose address is 0006h, is shown in Figure 1. When a maskable interrupt reaches the CPU, the corresponding flag bit of the IFR is set to 1, which indicates that the corresponding interrupt is pending or waiting for a response. Writing 1 to the corresponding flag bit clears the corresponding bit and clears its interrupt request. In Figure 1, 0 means that the number read is 0 under normal circumstances, R means reading, and W1C means clearing this bit to 0 when writing 1. -0 means this bit is 0 after reset.

(2) The 16-bit interrupt mask register (IMR), whose address is 0004h, is shown in Figure 2. It is used to mask external and internal hardware interrupts (except NMI and RS). When a hardware interrupt is to be masked, the corresponding bit is cleared to 0. When a hardware interrupt is to be enabled, the corresponding bit is set to 1, and each bit is not affected by hardware reset. In Figure 2, 0 indicates that the number read is 0 under normal circumstances, R indicates reading, W indicates writing, and -0 indicates that this bit is 0 after reset. Bit 2 is a timer interrupt, and a 1 indicates that the timer interrupt is open. . (3) The 16-bit interrupt control register (ICR), whose address is 0FFECh, is shown in Figure 3. Mainly used to control HOLD/INT1 and INT2/INT3. In Figure 3, when bit 0 is 0, it means masked interrupt 2 (INT2), when bit 0 is 1, it means open interrupt 2; when bit 1 is 0, it means masked interrupt 3 (INT3), when bit 1 is 1, it means open interrupt 3 ; Bits 2 and 3 are the flag bits of INT2 and INT3 respectively. When it is 1, it means that the corresponding interrupt has an interrupt request; when bit 4 is 1, it means the single edge trigger mode. When the falling edge of the INT1 pin arrives, an interrupt request is sent to the CPU. , used for INT1 interrupt. When bit 4 is 0, it indicates dual-edge trigger mode. This mode is suitable for HOLD operation.

　　In addition, TMS320F206 has two interrupts that cannot be operated and controlled by these three registers, namely: (1) RS (Reset). Once there is a request on RS, the program flow will be suspended and the program execution will be restarted from the program memory address. Start execution at 0000h. (2) NMI, when the NMI pin is activated, the program will be forcibly transferred to the interrupt vector at 24h, and other maskable interrupts will be disabled. Therefore, when the NMI pin is not in use, it should usually be set to a high level to avoid unexpected situations.

　　3 Interrupt implementation of TMS320F206

　　In actual application, the INT2 pin is used to measure the AC voltage frequency and phase, while the AC current phase is measured by the INT3 pin, and the phase difference between the voltage and current is calculated. In this example, the interrupt signals all use zero-crossing signals, the interrupt vector of the timer is timer, and the interrupt vector of INT2/INT3 is intp2 (the interrupt vector table is omitted). The main program flow chart is shown in Figure 4. The main program is as follows: start:nop setc intm; disable all interrupts splk #0ffffh,ifr; clear the interrupt flag splk #2h,imr; clear the interrupt flag splk #2h,imr; clear the mask bits of INT2 and INT3 splk #1h,60h out 60h,0ffech; only enable INT2 splk #0h,61h splk #0f9fh,62h; set timer out 61h,0fffah out 62h,0fff9h clrc intm; enable interrupt wait:idle b wait1; wait for interrupt interrupt INT2/3 service program (intp2 ) The flow chart is shown in Figure 5. The interrupt INT2/3 service program (intp2) is as follows: Intp2: setc intm; enter the INT2, INT3 interrupt service program. …… ; According to the control word, determine whether to enter the frequency test subroutine or the phase test subroutine bond intp23,tc b intp 21 intp23: in 60h,0fffech; Read the control word ICR bit 60h,13 sst #1h,62h bit 62h,4 ;Judge whether it is INT2 or INT3 bcnd intp22,tc interrupt b intp31 intp22:splk #0002h,60h ;INT2 service program out 60h,0ffech ;Enable INT3 interrupt splk #0c29h,63h out 63h,0fff8h ;Start timer splk #0002h,ifr ;Clear the flag bit of INT2/INT3 clrc intm ;Enable interrupt ret intp31:setc intm ;INT3 service program splk #0412h,64h out 64h,0fff8h ;Stop timer splk #0002h,ifr ;Clear the flag bit of INT2/INT3 clrc intm ret in 65h,0fffah; Read the time of the timer...; Calculate the phase intp21:setc intm; Determine the number of interrupts, turn on the first time...; Timer, turn off the timer the second time bchd stoptimerl,ntc out 63h,0fff8h; Start the timer splk #0002h, ifr; clear the INT2/3 flag clrc intm; turn on the interrupt ret stoptimer1: splk #0412h, 64h out 64h, 0fff8h; turn off the timer...; calculate the frequency b $; wait for the timer interrupt service routine ( timer) flow chart is shown in Figure 6. timer: lacl 73h; timer interrupt service routine... ; judge whether to enter the frequency test subroutine or the phase test subroutine according to the control word. cmpr 0 bcnd timer2,tc b timer1 timer1:lacl 69h ;Frequency timer service subroutine add #1h sacl 69h splk #4h,ifr ;Clear timer flag clrc intm ret timer2:lacl 69h ;Phase timer service subroutine add # 1h sacl 69h splk #4h,ifr; Clear the timer flag clrc intm ret; Interrupt return.