Implementation of 16th-order FIR filter based on DSP Builder

0 Introduction

FIR digital filter plays a very important role in various applications of digital signal processing. It can provide ideal linear phase response, obtain constant group delay over the entire frequency band, and thus obtain zero distortion output signal. At the same time, it can be implemented with a very simple algorithm. These advantages make FIR filter the first choice for design engineers. When using hardware description languages ​​such as VHDL or VerilogHDL to design digital filters. Since the program writing often cannot achieve good optimization, the filter performance is average, and the use of debugged IP Core needs to be purchased from Al-tera. Here, a FPGA design method based on DSP Builder is used to make the FIR filter design relatively simple and easy, and can meet the design requirements.

1 Introduction to FIR Filter

1.1 FIR filter principle

For a FIR filter system, its impulse response is always of finite length. The most specific FIR filter can be expressed as follows: Where r is the number of taps of the FIR filter; x(nr) is the delayed, r-tap input signal; b(r) is the number of taps of the rth level (unit impulse response); M is the order of the filter; y(n) represents the output sequence of the filter. The filter is to seek an achievable system function H(z) so that its frequency response H(ejω) satisfies the desired frequency domain signal, which can also be expressed in the form of convolution:

y(n)=z(n)*h(n)

A typical direct type I FIR filter is shown in Figure 1, and its output sequence y(n) satisfies the following equation:

1.2 Design requirements

The digital filter is actually a linear non-time-varying discrete system implemented by finite precision algorithm. Its design steps are to first determine its performance indicators according to the needs, design a system function h(n) to approximate the required performance indicators, and the coefficient calculation of the filter can be completed with the help of Matlab's powerful computing function and ready-made filter design tools, and finally implemented by finite precision algorithm. The design indicators of this system are: design a 16-order low-pass filter, select the sampling frequency Fs of the analog signal as 5 kHz, require the cutoff frequency Fc=1 kHz of the signal, and the bit width of the input sequence is 9 bits (the widest bit is the sign bit). The excitation source is a mixed signal of two signals with an amplitude of 27 and a frequency of 800 Hz and 1 600 Hz.

2 Design of FIR filter based on DSP Builder

2.1 Introduction to DSP Builder

DSP Builder is a system-level design tool for DSP development launched by Altera Corporation of the United States. It integrates Matlab and Simulink DSP development software in the QuartusⅡ design environment. The Matlab tool used in the past was only used for modeling DSP algorithms and simulation based on pure mathematics. Its mathematical model could not directly generate practical program code for the hardware DSP application system, and the results of simulation tests were often based on mathematical algorithm results. The traditional hardware description language-based design required by the previous FPGA was quite cumbersome because it took into account the connection between the delay of FPGA hardware and the VHDL recursive algorithm, as well as the complement operation and product result interception. As for DSP Builder, as a Simulink toolbox of Matlab, it enables the DSP system designed with FPGA to be modeled and simulated at the system level through the graphical interface of Simulink. The design model can be directly converted to VHDL hardware description language, and automatically call QuartusⅡ and other EDA design software to complete synthesis, netlist generation, device adaptation and even FPGA configuration download, so that the system description and hardware are organically integrated, fully reflecting the characteristics and advantages of modern electronic technology automation development. [page]

2.2 Design of FIR filter

2.2.1 FIR filter parameter selection

The filter designed by simulation using FDAtool, a filter design tool provided by Matlab, can meet the required FIR filter amplitude-frequency characteristics. Since floating-point decimals are difficult to implement in FPGA and the cost is too high, the filter coefficients and input data need to be converted into integers. The quantized system can be directly converted in the Matlab main window. For the input data, the gain multiplied by 28 is converted into integer input using the Altbus control bit width.

2.2.2 Establishment of FIR filter model

According to the principle of FIR filter, FPGA can be used to implement FIR filter circuit. The first step of DSP Builder design process is to input the design in Matlab/Simulink, that is, to create an MDL model file in Matlab's Simulink environment, and to call the graphic modules in DSP Builder and other Simulink libraries in a graphical way to form a system-level or algorithm-level design block diagram, as shown in Figure 2.

2.2.3 Simulation in Simulink and Generation of VHDL Code

After completing the model design, you can simulate the model in Simulink first, and you can view the intermediate results of each step through the oscilloscope module in Simulink. The input signal uses the superposition of two sinusoidal signals with the same amplitude of 800 Hz and 1 600 Hz. The simulation results are shown in Figure 3. It can be seen from the simulation waveform that after passing through the filter, the 1 600 Hz signal can be well filtered out.

Double-click SignalCompiler to analyze the above design model, select the corresponding chip, and "translate" the above design module diagram file into VHDL language.

2.2.4 RTL simulation with Modelsim

The simulation in Simulink is of the nature of system verification, which is a simulation of the mdl file, and does not simulate the generated VHDL code. In fact, the generated VHDL describes the RTL level, which is for the specific hardware structure, while the model simulation in Matlab's Simulink is at the algorithm level. There may be differences in software understanding between the two, and the converted VHDL code implementation may not be completely consistent with the situation described by the mdl model. This requires functional simulation of the generated RTL-level VHDL code, and the simulation results are shown in Figure 4.

The simulation results show that the simulation results in Modelsim are basically consistent with those in Simulink, and the filter has a good filtering effect. It can be seen that after the input sine wave is digitized, the analog waveform can be restored in Modelsim. It meets the design requirements and can be used for hardware design in the QLtortusⅡ environment.

2.2.5 Implementation of filter on FPGA

In the QuartusⅡ environment, open the QuartusⅡ project file created by DSP Builder, and simulate again in QuartusⅡ, so that you can see the timing waveform that meets the requirements. Then specify the device pins, compile, and finally download to the FPGA device, you can test the hardware, add the clok signal and enable signal, use the signal generator to generate the required two sine signals of different frequencies, and you can see the filtered results on the oscilloscope. If you need to design different filter circuits, you only need to modify the FIR filter model file to achieve it. This not only avoids the tedious VHDL language programming, but also facilitates adjustment.

3 Conclusion

When developing digital filters using FPGA, using DSPBuilder as a design tool can speed up the process. Of course, in actual applications, the converted VHDL may be further optimized due to the influence of accuracy, speed and device selection.