DSP Basics

Digital Signal Processing
As a case study, let's consider one of the most common functions in the digital world: filtering. Simply put, filtering is
the processing of a signal to improve its characteristics. For example, filtering can remove noise or static interference from a signal, thereby improving its signal-
to-noise ratio. Why use a microprocessor instead of analog devices to filter signals? Let's look at the advantages:
The performance of analog filters (or more generally, analog circuits) depends on environmental factors such as temperature. Digital filters
are basically unaffected by the environment.
Digital filtering is easy to replicate within very small tolerances because its performance does not depend on
a combination of devices whose performance has deviated from the normal value.
Once an analog filter is manufactured, its characteristics (such as the passband frequency range) are not easy to change. Using a microprocessor
to implement a digital filter, the filter characteristics can be changed by reprogramming it.
Comparison of signal processing methods
Comparison factors Analog method Digital method
Flexibility of design modification Modify hardware design, or adjust hardware parameters Change software settings
Precision Components Precision A/D bit number and computer word length, algorithm
Reliability and repeatability are affected by ambient temperature, humidity, noise, and are not affected by these factors
Interference and influence of electromagnetic fields, etc. are large
Large-scale integration Although there are some analog integrated circuits, there are fewer varieties, low integration, and high prices DSP devices
Small size, strong functions, low power consumption, good consistency, easy to use, high performance/price ratio
Real-time Except for the delay introduced by the circuit, the processing is real-time and is determined by the processing speed of the computer
High-frequency signal processing can process microwave, millimeter wave and even light wave signals According to the requirements of the Nye criteria, it is limited by S/H, A/D
and processing speed
Digital Signal Processor
Classification of microprocessors
General-purpose processors (GPP)
use von Neumann structure, and the storage space of programs and data is combined into one
8-bit Apple (6502), NEC PC-8000 (Z80)
8086/286/386/486/Pentium/Pentium II/ Pentium III
PowerPc 64-bit CPU (SUN Sparc, DEC Alpha, HP)
CISC complex instruction set computer, RISC reduced instruction set computer
Various methods are used to improve the computing speed, such as increasing the clock frequency, high-speed bus, multi-level Cashe, coprocessor, etc.
Single Chip Computer/ Micro Controller Unit (MCU)
In addition to the ALU and CU of the general CPU, there are also memory (RAM/ROM) registers, clocks, counters,
timers, serial/parallel ports, and some also have A/D, D/A
INTEL MCS/48/51/96 (98)
MOTOROLA HCS05/011
DSP
adopts Harvard structure, and the program and data are stored separately
A series of measures are adopted to ensure the processing speed of digital signals, such as special optimization of FFT
Simple comparison between MCU and DSP
MCU DSP
low-end high-end low-end high-
end Instruction cycle (ns) 600 40 50 5
Multiply-Add Time (ns) 1900 80 50 5
US$/MIPS 1.5 0.5 0.15 0.1
Comparison of DSP Processors and General Purpose Processors
Consider an example of digital signal processing, such as a finite impulse response filter (FIR). In mathematical terms, an FIR filter
is a series of dot products. It takes an input quantity and an ordinal vector, multiplies the coefficients and a sliding window of input samples
, and then adds all the products together to form an output sample.
Similar operations occur repeatedly in the digital signal processing process, making it necessary for devices designed for this purpose to provide specialized support
, which has led to the split between DSP devices and general purpose processors (GPPs):

1 Support for dense multiplication operations
GPP is not designed to do dense multiplication tasks. Even some modern GPPs require multiple instruction cycles to do a
multiplication. DSP processors use dedicated hardware to implement single-cycle multiplication. DSP processors also add accumulator registers
to handle the sum of multiple products. Accumulator registers are usually wider than other registers, adding extra bits called result bits
to avoid overflow.
At the same time, in order to fully realize the benefits of dedicated multiplication-accumulation hardware, almost all DSP instruction sets include explicit
MAC instructions.

2 Memory Structure
Traditionally, GPP uses the von Neumann memory structure. In this structure, there is only one memory space
connected to the processor core through a set of buses (one address bus and one data bus). Usually, 4 memory accesses will occur for a multiplication
, which takes at least four instruction cycles.

Most DSPs use the Harvard architecture, which divides the memory space into two, one for program and one for data. They have two
sets of buses connected to the processor core, allowing them to be accessed simultaneously. This arrangement doubles the bandwidth of the processor memory and,
more importantly, provides both data and instructions to the processor core at the same time. With this layout, the DSP can implement single-cycle MAC
instructions.
Another problem is that the typical high-performance GPP now actually contains two on-chip caches, one for data and
one for instructions, which are directly connected to the processor core to speed up access at runtime. Physically, this on-chip
dual memory and bus structure is almost the same as the Harvard architecture. Logically, however, there are important differences between the two
.
GPPs use control logic to determine which data and instruction words are stored in the on-chip cache, which the programmer does not
specify (and may not even know). In contrast, DSPs use multiple on-chip memories and multiple sets of buses to ensure
multiple accesses to memory per instruction cycle. When using DSPs, programmers must explicitly control which data and instructions are stored
in on-chip memory. When writing programs, programmers must ensure that the processor can effectively use its dual buses.

In addition, DSP processors almost never have data caches. This is because the typical data of DSP is a data stream. That is
, after the DSP processor calculates each data sample, it is discarded and rarely reused.
3 Zero-overhead loops
If you understand a common feature of DSP algorithms, that most of the processing time is spent on executing smaller loops,
it is easy to understand why most DSPs have dedicated hardware for zero-overhead loops. The so-called zero-overhead loop
means that when the processor executes the loop, it does not spend time checking the value of the loop counter, conditionally transferring to the top of the loop, and decrementing
the loop counter by 1.

In contrast, GPP loops are implemented in software. Some high-performance GPPs use branch prediction hardware to achieve nearly
the same effect as hardware-supported zero-overhead loops.

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4 Fixed-point calculations
Most DSPs use fixed-point calculations instead of floating-point. Although DSP applications must pay great attention to digital accuracy,
it should be much easier to use floating-point, but for DSP, cheapness is also very important. Fixed-point machines
are cheaper (and faster) than corresponding floating-point machines. In order to avoid using floating-point machines while ensuring digital accuracy, DSP processors
support saturation calculations, rounding, and shifting in both instruction sets and hardware.

5 Specialized addressing modes
DSP processors often support specialized addressing modes that are useful for common signal processing operations and algorithms.
For example, block (loop) addressing (useful for implementing digital filter delay lines) and bit-reversal addressing (useful for FFT).
These very specialized addressing modes are not often used in GPP and can only be implemented in software.

6 Prediction of Execution Time
Most DSP applications (such as cell phones and modems) are strictly real-time applications, where all processing must
be completed within a specified time. This requires the programmer to determine exactly how much processing time each sample will take, or, at least
, to know how much time it will take in the worst case.

If you plan to use a low-cost GPP to complete real-time signal processing tasks, the prediction of execution time will probably not be a
problem, because low-cost GPPs have a relatively straightforward structure and it is easier to predict the execution time. However, most real-time
DSP applications require processing power that low-cost GPPs cannot provide.

The advantage of DSPs over high-performance GPPs at this point is that even with cached DSPs,
the programmer (not the processor) decides which instructions go in, so it is easy to tell whether instructions are
read from cache or memory. DSPs generally do not use dynamic features such as branch prediction and speculative execution. Therefore, it is completely straightforward to predict the required execution time for a given piece of code
. This allows the programmer to determine the performance limits of the chip.

7 Fixed-point DSP instruction set
The fixed-point DSP instruction set is designed with two goals in mind:
enabling the processor to complete multiple operations in each instruction cycle, thereby improving the computational efficiency of each instruction cycle. Minimizing the memory space required to store DSP programs (this issue is particularly important in cost-sensitive DSP applications
, as memory has a significant impact on the cost of the entire system ).

To achieve these goals, the instruction set of DSP processors usually allows the programmer to specify several parallel
operations in one instruction. For example, a single instruction contains MAC operations, that is, one or two data moves at the same time. In a typical example
, a single instruction contains all the operations required to calculate one section of an FIR filter.
The price paid for this high efficiency is that its instruction set is neither intuitive nor easy to use (compared to the GPP instruction set).

GPP programmers usually don't care whether the processor's instruction set is easy to use, because they usually use
high-level languages ​​such as C or C++. Unfortunately for DSP programmers, most DSP applications are written in assembly language
(at least partially assembly language optimized). There are two reasons for this: First, most widely used high-level languages, such as
C, are not suitable for describing typical DSP algorithms. Second, the complexity of the DSP structure, such as multiple memory spaces, multiple
buses, irregular instruction sets, highly specialized hardware, etc., makes it difficult to write efficient compilers for it.

Even if the compiler is used to compile the C source code into DSP assembly code, the optimization task is still heavy. Typical DSP applications
have a large number of computing requirements and strict overhead constraints, making program optimization essential (at least for the
most critical parts of the program). Therefore, a key factor in considering the selection of DSP is whether there are enough programmers who can adapt well to
the DSP processor instruction set.

8 Development Tool Requirements
Because DSP applications require highly optimized code, most DSP vendors provide some development tools to help programmers
complete their optimization work. For example, most vendors provide processor simulation tools to accurately simulate
the processor's activities within each instruction cycle. These are very useful tools for both ensuring real-time operation and code optimization.
GPP vendors usually do not provide such tools, mainly because GPP programmers usually do not need this level of detailed
information. The lack of GPP simulation tools that are accurate to the instruction cycle is a big problem faced by DSP application developers: since
it is almost impossible to predict the number of cycles required for a high-performance GPP for a given task, it is impossible to explain how to improve the performance of the code.