Offline Video Encoding/Decoding System Based on DSP

The ADV611 chip is a codec chip produced by ANALOG DEVICES, USA, which uses wavelet algorithm to perform real-time compression/decompression processing on video images. This chip not only integrates video codec algorithms, but also provides real-time adjustment means for data compression effect, and the data output rate can be flexibly controlled. This article introduces an offline video codec system based on the ADV611 chip and combined with TI's DSP chip TMS320C542.

In this offline video image codec system, DSP, as the control core, on the one hand, manages ADV611, memory, peripheral control microcontroller and communication interface, and on the other hand, adjusts the image compression effect of ADV611 and controls the data rate in real time. How DSP can efficiently complete these control tasks is the key to the realization of this video codec system. Since TMS320C542 has high-speed computing power and rich interface resources, it is a high-speed microprocessor that integrates data processing and communication functions, so the DSP of this system chooses TMS320C542.

1 System overall structure

Figure 1 shows the overall structure block diagram of the system. In Figure 1, the original PAL format ( 720×288@50 frames/second) video signal is converted into a CCIR656 format (8-bit 27MHz) data stream through the video A/D at the image acquisition end, and then wavelet compression coding is performed through ADV611.A. DSP.A reads the image data from ADV611.A and caches it in the data memory. According to the rate of the communication device, DSP.A sends the compressed and coded image data to the image playback end through the user's communication device through the communication serial interface. After receiving the data from the serial interface, DSP.B at the image playback end caches it in the memory first, and then sends the compressed video data to ADV611.B for decompression according to the data request of ADV611.B. The image data restored by ADV611.B is still sent to the video D/A in the standard format of CCIR656 to be converted into a video analog signal, and finally played back by the monitor.

This offline video encoding/decoding system is designed with the remote control function of the image acquisition front end by the user at the far end of the image playback. At the image playback end, the user sends the control command to the single-chip microcomputer B through the controller, and then these commands are sent to the DSP.A of the image acquisition front end through DSP.B and the communication device. DSP.A divides the control commands into two categories. The first category is the adjustment commands of image brightness, contrast, color saturation and camera focal length and pan/tilt motion. DSP.A notifies single-chip microcomputer A, and finally single-chip microcomputer A controls the video A/D chip and the camera to complete the command. The other category of commands is the command to adjust the image frame rate and wavelet image processing effect. DSP.A directly sets the relevant registers of ADV611.A to implement the command.

2 DSP and video wavelet encoding/decoding chip ADV611

In the image acquisition end and image playback end of this system, ADV611 is connected to the address data bus of the DSP chip as the I/O port device of TMS320C542. Through this interface, DSP can read and write the internal control register of ADV611, and can read and write image compression data to ADV611. The control registers inside ADV611 include three categories. The first category is used to set the working status of ADV611, which includes image encoding status, image decoding status, image processing format, etc. The second category of registers can provide statistical information for each frame of image. They are all read-only registers, and the statistical information provided includes the maximum, minimum, and total brightness, as well as the amount of compressed data for each frame of image, etc. The last category of registers is the control register for data encoding and compression. The FIFO inside ADV611 is used to control the reading and writing operations of image compression data, and can give FIFO full empty, partially full, and full signals.

All processing request signals of ADV611, including image compression data access request, each frame of statistical data ready, and data flow error, share an interrupt request to send to DSP. Figure 2 shows the processing flow after DSP.A responds to an interrupt, taking the image acquisition end as an example. DSP.A first reads the interrupt flag register inside ADV611.A, further analyzes the cause of the interrupt, and then processes it. Because it takes a long time to process image compression data, in order to prevent the new processing application of ADV611.A from being missed during image data processing, DSP.A reads the ADV611 interrupt flag register again after reading the encoded data and writing it into the memory.

DSP.A calculates the control parameters of the image compression encoding effect of the acquisition end ADV611.A in the main program. ADV611 provides users with three means of controlling image effects and data flow through control registers. The first is to set the quantization coefficient, that is, to achieve the purpose of data compression by changing the quantization weights of the data in different frequency bands after wavelet decomposition. The second compression method is frame reduction. ADV611 can reduce from 50 frames/second to 2 frames/second. The last compression method is quality frame control. ADV611 can set another display area in a frame of 720×288 and attenuate the image outside the area, thereby compressing the data by reducing the effective frame size. The setting of the display area size is achieved by adjusting the quality frame data inside ADV611. In the main program, DSP.A will calculate and modify the control register parameters in ADV611.A according to the user's adjustment command. 3 DSP and single-chip microcomputer The system's control and management of video A/D, D/A, camera and user controller are all slow. As a high-speed microprocessor, DSP is not suitable for wasting a large number of instruction cycles to process these slow controls. Moreover, TMS320C542 does not have flexible control I/O ports. Therefore, this system selects a single-chip microcomputer to assist TMS320C542 in completing low-speed control. TMS320C542 provides a host control interface HPI[1], which can easily realize data communication between DSP and single-chip microcomputer. For example, at the image playback end, when single-chip microcomputer B receives a user control command, it fills the command data into the specified data area of ​​DSP.B through HPI, and then issues an HPI interrupt request to request DSP.B to process. This process will not affect the program task being executed by DSP.B. When DSP.A at the image acquisition end has a control command to be transmitted to single-chip microcomputer A, it first writes the command code data into the specified data area inside the DSP, and then triggers an interrupt of single-chip microcomputer A through an output signal of the HPI interface, requesting single-chip microcomputer A to process. In the interrupt of single-chip microcomputer A, single-chip microcomputer A reads the command data in the data area specified by DSP through HPI, and then executes the corresponding command operation.

4 DSP and memory and communication interface

The serial communication interface of this system is implemented by using the buffered serial port BSP of TMS320C542[1] plus an auxiliary interface driver circuit. After the DSP sets the send buffer and receive buffer, the BSP can automatically send and receive data in the buffer, thus improving the processing efficiency of the DSP. Since this system needs to adapt to the transmission rate of the communication device selected by the user, the serial communication interface of the system based on BSP works in a passive mode.

In order to ensure that image data will not be read empty or blocked during transmission, the system adopts ping-pong buffer and ring buffer technology. Taking the data transmission of the image acquisition end as an example, the transmission buffer of the image compression encoding data adopts the structure of Figure 3. As shown in Figure 3, the two transmission buffers 1 and 2 form a ping-pong buffer structure under the control of the selection mechanisms C and D. When the mechanism D selects a transmission buffer and automatically sends data through the BSP serial interface, the selection mechanism C prepares the data in the other transmission buffer. In the design, the writing speed of the transmission buffer is greater than the maximum communication speed of the user, that is, greater than the reading speed of the buffer, so this ping-pong buffer first avoids the possible data transmission reading problem in the communication interface.

The frame image buffers 1, 2 and 3 actually constitute a ring storage structure, that is, under normal circumstances, the mechanism A is selected to continuously fill the compressed image data from ADV611 into the buffer in units of one frame in the order of 1-2-3-1 cycle. Similarly, the mechanism B reads the data in the buffer in the order of 1-2-3-1. In principle, the read pointer of the data in the frame image buffer should lag behind the write pointer by one buffer. For example, when a frame of image data is sent out through the mechanism B, if the mechanism A is writing to the buffer 3, the reading of the new frame of data to be sent will start from the buffer 2. This strategy further ensures that the transmission will not be read empty. However, if the communication rate drops, the read pointer is in the buffer 2, and the data writing has updated the two frames of images in the buffer 3 and 1, the mechanism A will refill the new frame of data into the buffer 1 instead of the buffer 2, thereby avoiding data blocking conflicts. The events of writing to the same buffer for the second time and reading out of the same buffer for the second time respectively indicate that the image compression data flow is greater than the communication rate and the image compression data flow is less than the communication rate. Based on this fact, the DSP will dynamically adjust the image compression ratio to balance the image compression data flow and the communication rate.

Of course, the use of buffering technology to ensure the reliability of image data transmission is at the expense of the real-time nature of the image.

5 Overall software structure of DSP in the system

The key to the design of the DSP control program of this offline video encoding/decoding system is how to efficiently coordinate and complete various control tasks to avoid unexpected interruptions in image data transmission caused by improper task process arrangement. Taking the image acquisition end as an example, as shown in Figure 4, the DSP program processes BSP data transmission and data reception control and ADV611 service requests as interrupts to improve the response speed of these tasks. In particular, in order to avoid data loss in the communication serial port, the program allows BSP transmission interrupts and reception interrupts to occur and respond immediately in the ADV611 service request interrupt. In the main loop part of the program, the DSP completes the tasks of writing data to the transmission buffer, reading data from the reception buffer, calculating image compression encoding parameters, and sending commands to the microcontroller through a series of state judgments.

The DSP design method described in this paper, as the core of the offline video encoding/decoding system, realizes the effective control of the real-time system in practical applications, ensures the reliable transmission of image data, and completes the user's remote control function. Through actual measurement, this design allows the DSP to have a lot of idle time, and the clear software structure makes it easy to add new functional algorithms, such as moving target detection alarm and moving target tracking algorithms, thereby further enriching the functions of the system.