PCM30/32-channel system simulation based on Max+ PlusⅡ

Abstract: PCM is a common method for converting analog signals into digital signals. In order to study the timing and frame structure of the PCM30/32-channel system, the circuit diagram of the system was designed using Max+ Plus Ⅱ, and the circuit was simulated in Max+ Plus Ⅱ. The simulation results show that the PCM 30/32-channel system contains 32 channels of information, including 30 voice signals and two synchronous information. Each channel of information can be represented by D1~D8 eight-bit PCM code . The software is easy to use, flexible to operate, supports many devices, and has flexible design input methods.

In order to obtain the maximum economic benefits in communication technology, it is necessary to make full use of the transmission capacity of the channel and expand the communication capacity. Therefore, adopting a multiplexing system is an extremely important means of communication. The most commonly used multiplexing systems are frequency division multiplexing (FDM) communication system and time division multiplexing (TDM) communication system. Frequency division multiplexing technology uses sinusoidal carriers of different frequencies to modulate the baseband signal, move the spectrum of each baseband signal to different frequency bands, and transmit it on the same channel. In the time division multiplexing system, the baseband signal is sampled using pulses of different time sequences, and the sampled pulse signals are arranged in time sequence and transmitted on the same channel. Frequency division multiplexing is mainly used in analog communication systems, and time division multiplexing is often used in digital communications. Code division multiplexing (CDMA) is used for mobile communications.

1 EDA Technology

EDA ( Electronic Circuit Design Automation) is an automated design process for electronic products that uses computers as working platforms, hardware description languages ​​( VHDL ) as design languages, programmable devices (CPLD/FPGA) as experimental carriers, and ASIC /SOC chips as target devices to perform necessary component modeling and system simulation . EDA is a revolution in the field of electronic design, which originated from computer-aided design, computer-aided manufacturing, computer-aided testing, and computer-aided engineering. Using EDA tools, electronic designers design electronic systems from concepts, algorithms, and protocols. The entire process from circuit design, performance analysis to IC layout or PCB layout generation can be automatically completed on computers. EDA represents the latest development direction of today's electronic design technology. Its basic feature is that designers use computers as tools to design and divide the entire system according to a top-down design method, complete the system behavior level design using hardware description language, and use advanced development tools to automatically complete logic compilation, simplification, segmentation, synthesis, optimization, layout and routing, simulation, and adaptation compilation and programming download of specific target chips. This is called a high-level design method for digital logic circuits .

Main features of EDA technology As the leading technology in modern electronic system design, EDA has the following obvious features:

(1) Using software design methods to design hardware; (2) Chip-based design methods; (3) High degree of automation; (4) Automatic product design.

2 PCM Transmitter Timing and Frame Structure

For voice signals, CCITT stipulates that the sampling rate of PCM is 8 kHz, that is, the information can be divided into 8K frames within 1 second. The period of each frame is 125 seconds. In each frame period, 32 time slots are inserted, represented by TS0~TS31, among which TS0 is used as a frame synchronization time slot to transmit frame synchronization code groups and frame loss synchronization report codes, TS16 is used to transmit multi-frame synchronization signals, multi-frame loss synchronization reports and various channel signals, and the other 30 time slots are used to transmit 30 voice signals. Each time slot can be inserted with 8-bit binary information code (that is, each time slot contains 8 bits of information code, which is completed by the PCM encoder ). In addition, every 16 frames form a multiframe, that is, there are 16 subframes in a multiframe (numbered F0, F1, ..., F15), of which F0, F2, F14 are even frames, and F1, F3, ..., F15 are odd frames. The above frames constitute the PCM30/32 road group system. The frame structure of PCM is shown in Figure 1.

Figure 1 Frame structure of PCM30/32 road-based group system

According to the above frame structure, the code rate of the PCM30/32 system is:

Fs = 8K × 32 × 8 = 2.048 Mb/s The synchronization code and signaling bits of the above frame structure are as follows:

(1) TS0 of the even frame (F0, F2,…, F14) is used to transmit the frame synchronization code, and the code type is 0011011.

(2) 1b in T S0 of odd frames (F1, F3, ..., F15) is used to transmit the frame desynchronization code. When the frame is synchronized, A1 = 1, and when it is desynchronized, A1 = 0. The other bits are used for domestic communication.

(3) The first bit of each subframe TS0 is used for CRC check and is always set to “1” when not in use.

(4) TS1~TS15 and TS17 ~TS31, a total of 30 time slots, are used to transmit information signals from channel 1 to channel 30.

(5) TS16 is used to transmit multiframe synchronization signals, multiframe desynchronization signals and various channel (on-hook, busy, etc.) signals.

From the frame structure of PCM, we know that the timing of PCM base group is controlled by clock and frame timing generator , and its principle block diagram is shown in Figure 2. The PCM encoding in the figure is completed by a single-chip PCM encoder, and the code type converter is an NRZ code HDB3 code converter. The converted bipolar signal code is sent to the digital modulator or multi-channel base group multiplexer, and then multiplexed into a high-order group and sent to the digital modulation device or optical communication equipment.

Figure 2 PCM30/32 base group system principle block diagram

3 Simulation Results

Open the Max+ Plus software on the PC interface, input the circuit diagram shown in Figure 3; select the menu File \ Project \ Set Project to Current File, and then select the menu Max+ plus \ compiler to edit the current graphic file; simulate the circuit and record the circuit simulation waveform (simulation parameters are grid size = 2.4 s; End time = 100 ms). The simulation results are shown in Figures 4 and 5.

Figure 3 PCM30/32 base group system circuit diagram

Figure 4 PCM30/32-channel system transmitter timing and frame structure simulation results 1

Figure 5 PCM30/32-channel system transmitter timing and frame structure simulation results 2

As can be seen from Figure 4 and Figure 5, the simulation results include three frames of information, F0, F1, and F2. Each frame contains 30 channels of information, ch1 to ch30. Each channel of information can be represented by eight-bit PCM codes, D1 to D8.

4 Conclusion

This paper uses Max+ Plus software to simulate the timing and frame structure of the PCM30/32-channel system. The simulation results clearly show the rules of the system's timing. The software is easy to use, flexible to operate, supports many devices, and has flexible and changeable design input methods.