Design and verification of 3.125G serial transmission system based on V5

1 Introduction

With the continuous development of electronic systems, the demand for data transmission between chips and boards is also growing. The traditional single-ended parallel data transmission mode can no longer meet the requirements of current high-bandwidth applications. The release of new serial specifications such as USB 3.0, SATA 3.0, PCI-E 2.0 and the introduction of higher-speed serial-to-parallel/serial-to-parallel conversion unit (SERDES) chips have aroused the industry's infinite longing for high-speed differential serial data transmission. In order to solve the huge data throughput requirements brought by multi-antenna (MIMO) signal processing in the next generation of wireless communication base stations, this paper presents a design scheme based on the GTP unit of Virtex-5 FPGA to achieve 3.125Gbps serial transmission on a single pair of differential lines in the Advanced Telecommunications Computing Architecture (ATCA) chassis.

2 Transmission system design

The structure of the transmission system is shown in Figure 1. It mainly consists of two ATCA boards and an ATCA chassis backplane. An FPGA is placed on each of the two ATCA boards as the two endpoints of the serial link. The two FPGAs are connected by two pairs of differential lines to form a bidirectional 3.125Gbps serial communication link. In order to verify the long-distance transmission capability of the system, the two boards are placed in physical slots 1 and 14 of the 14-slot ATCA chassis. At this time, the total transmission distance is about 40 inches.

Figure 1 Overall structure of a high-speed serial transmission system

Since the backplane performance of the existing ATCA chassis cannot be changed, the main design of this paper focuses on the design of the ATCA board, mainly the stacking design of the board, the power supply design of the FPGA as the transmission endpoint, the reference clock design of serial transmission, and the parameter adjustment of the GTP transceiver unit inside the FPGA.

2.1 Stackup Design

The stacking design is the basis of other designs. This system mainly considers two aspects when designing the stacking structure: First, all GTP transceiver differential lines are laid on the stripline signal layer instead of the single-side coupled microstrip signal layer. Although the stripline has a larger loss than the microstrip line, the impedance of the stripline is more controllable, and the coupling with the AC ground plane is better, which is conducive to the return of high-speed signals; second, in order to reduce the power supply noise of the GTP unit, three power planes are used to supply power to the three analog power supplies AVTT (termination power supply), AVCC (internal circuit power supply), and AVPLL (PLL power supply) of the serial transceiver. The specific stacking structure is shown in Figure 2.

Figure 2 Design of stacked structure

2.2 Power Supply Design

The noise of GTP analog power supply is one of the important factors affecting GTP performance. In addition to allocating the three analog power supplies of GTP to a separate plane and coupling them with a ground plane when designing the stack, a magnetic bead is connected in series to each power pin externally, and a 0.22μf capacitor is connected in parallel to form an LC low-pass filter to filter the power supply. The analog power supply of GTP is supplied by the low-noise LDO power chip TPS74401, and the output voltage ripple is less than 50mV.

2.3 Clock Design

The reference clock of high-speed serial transceivers is another important factor affecting the quality of signal transmission. This system uses the clock synthesis chip LMK03001C with a powerful clock clean function to generate the reference clock of the serial transceiver. The maximum root mean square jitter (RMS jitter) of its output clock is less than 550fs, the duty cycle is 50%, and the output clock level standards are LVDS and LVPECL. The frequency of its output clock can be flexibly programmed to meet the requirements of different transmission rates, so that this system can adapt to the implementation of various serial transmission protocols.

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2.4 Pre/de-emphasis and equalization parameter design

In order to combat the excessive attenuation of high-frequency components by the transmission path, it is necessary to perform pre-emphasis at the transmitter or add equalization at the receiver, or use both methods at the same time. Both pre-emphasis and linear equalization improve the quality of the received signal by distorting the signal. Only the appropriate ratio of pre-emphasis and linear equalization and the combination of the two can achieve the purpose of improving the quality of the received signal, otherwise it will deteriorate the quality of the received signal. This paper uses the SPICE model of GTP and the S parameter model of the serial transmission channel to simulate the transmission quality of the serial link under different pre-emphasis and equalization parameter settings, so as to find the appropriate parameter settings.

Figure 3 Transmitted signal at different pre-emphasis/de-emphasis ratios

Figure 3 is a simulation result diagram under different pre-/de-emphasis ratio settings. The middle part shows the transmission waveform of three consecutive high-level bits. Obviously, the amplitude of the last two high-level bits decreases accordingly with the pre-/de-emphasis ratio. In addition, the signal level in the same logic bit in the figure is not flat. This phenomenon is mainly caused by the emission caused by the impedance mismatch on the signal transmission link, such as the connector connection between the ATCA board and the ATCA backplane.

Figure 4 Effects of pre-emphasis/de-emphasis and equalization on received signals

Figure 4 shows the eye diagram of the received signal of GTP under different parameter settings. The first sub-figure is the signal eye diagram on the FPGA pin of the receiving end when no pre-/de-emphasis is applied at the transmitting end. It can be seen that long-distance transmission seriously deteriorates the quality of the signal, and the signal eye diagram tends to be closed. The second sub-figure is the signal eye diagram on the FPGA pin of the receiving end when 23% pre-/de-emphasis is applied at the transmitting end. Pre-/de-emphasis compensates for the low-pass characteristics of the transmission channel to a certain extent, reduces the jitter of the signal, and improves the quality of the signal. The third sub-figure is the case where no pre-/de-emphasis is applied at the transmitting end and 25% equalization is applied at the receiving end, that is, 75% of the original signal plus 25% of the output of the high-pass filter is used as the total received signal. Just like pre-/de-emphasis, through equalization, the high-frequency component is relatively enhanced and the low-frequency component is relatively suppressed, which effectively compensates for the imperfection of the channel. The fourth sub-figure is the received signal obtained when 4.5% pre-/de-emphasis and 25% equalization act simultaneously. It can be seen that the effective combination of pre-emphasis/de-emphasis and equalization can greatly improve the transmission signal that was originally severely deteriorated.

3. Verification and discussion of results

The performance test of this system is mainly carried out in two ways: one is to collect the eye diagram of the signal at the transmitting and receiving ends and compare it with the wave mask (EYE_MASK) of the receiver; the other is to test the bit error rate of serial transmission (BERT: bit error ratio test).

The receiver's EYE_MASK vividly reflects the receiver's sensitivity and dynamic range. Only signals within the receiving area can be correctly identified by the receiver, otherwise the sampling judgment will result in bit errors. The minimum EYE_MASK of the GTP unit in Virtex-5 is (112ps, 150mV), where 112ps represents the minimum eye width (EYE_WIDTH) and 150mV gives the minimum eye height (EYE_HEIGHT). Figure 5 shows the signals at both ends of the serial transmission measured near the FPGA transmit pin and receive pin. In this test channel environment, the normal transmission signal has been greatly attenuated and distorted when it reaches the receiving end, with an eye width of only 96ps and an eye height of only 70.5mV, both of which do not meet the GTP requirements (112ps, 150mV). If the equalizer inside the chip is not considered, the received signal will not be correctly identified. On the contrary, if pre-emphasis/de-emphasis is added at the transmitting end, it can effectively combat the channel imperfections and reduce the jitter of the signal at the receiving end to a certain extent, so that the eye opening reaches (211ps, 191mV). This measured result is consistent with the previous simulation and theoretical analysis.

Figure 5 Measured serial signal eye diagram

Xilinx provides a tool called IBERT specifically for bit error rate testing, as shown in Figure 6. Its basic principle is to send a pseudo-random sequence (such as PRBS7) at the transmitter, and then calibrate the sequence with the same pseudo-random sequence after receiving it at the receiver, and record the calibration result. This tool can be used to dynamically adjust the GTP parameter settings and measure the corresponding transmission bit error rate.

Figure 6 Bit error rate test

The IBERT tool can be used to obtain the error-free (BER < 1e-12) sampling interval of this system under different pre-emphasis/de-emphasis and equalization parameter settings, as shown in Table 1.

Table 1 Error-free sampling interval (unit: 1/128UI)

Conclusion

Through simulation, theoretical analysis and actual test verification, this paper presents a design and verification scheme for a serial transmission system based on Virtex-5, achieving long-distance 3.125Gbps serial transmission.