Interface Design between VC5402 and External Memory

As an important gateway for DSP chips to exchange data with the outside world, the quality of the external memory interface directly affects the adaptability and control function of DSP. At the same time, a high-performance and flexible external memory interface is also an important guarantee for building an image acquisition and processing system using DSP. Based on the above reasons, this paper proposes a CPLD-based VC5402 memory expansion solution, which has the advantages of flexible interface and convenient debugging.

Resource configuration in image acquisition and processing system

In order to more conveniently understand the interface design between VC5402 and external memory, this paper first introduces the resource configuration status of VC5402 in the designed image acquisition and processing system.

VC5402 has 3 bits (MP/MC#, OVL Y, DROM) that together affect the memory structure. Users can modify the value of PMST to configure the storage space as needed.

This paper adopts the microprocessor mode, sets MP/MC# = 1, and the 4k-word ROM on the chip is not mapped to the program area, that is, the ROM is inaccessible. Set OVL Y = 0, the 16k-word RAM on the chip is not mapped to the program memory, so that the 64k-word program storage space is fully configured as external memory, and two SRAMs (recorded as SRAM1 and SRAM2) are used to store the collected image data.

Each time the DSP performs a reset, the DROM is cleared and the setting of this bit is not changed in the system. In this way, the lower 48k words of the data storage space all correspond to the external memory, of which the lower 32k words are mapped to the external FLASH to store the boot program, interrupt vector table, user code, etc. The other 16k words are mapped to SRAM (denoted as SRAM3) to store the results of data processing.

The delay required for expanding program storage space and data storage space can be set by software programming to the DSP wait state register (SWWSR) to achieve the fastest speed. This avoids the use of hardware for handshake communication and simplifies the interface design.

Program memory expansion

The actual amount of image data collected in the system is about 1 M × 8 b, while the data space of VC5402 is only 64 k words, and VC5402 has 16 k words of random access memory and 4 k words of read-only memory, which is far from meeting the storage requirements. Therefore, the data space needs to be expanded to 1 MB to realize the storage of image data. Since the program space of VC5402 can be expanded to 1 M × 16 b, and there are special instructions for accessing the extended memory. Considering the complexity of data space expansion, we store the collected image data directly in the extended program space. Two SRAMs (IS61LV5128AL-12) are selected in the system to store raw data. The IS61LV5128AL-12 chip is a 512 k × 8 b high-speed CMOS static memory with an access speed of 12 ns.

The design of the implementation scheme of the two-chip memory interface is shown in Figure 1. Among them, SRAM-CE1, SRAM-CE2, OE, and WE are the chip select signal, read enable signal, and write enable signal of the two SRAMs respectively. These logic combinations are implemented by CPLD. The simulation waveform is shown in Figure 2.

When the program space is expanded, bits A (0) to A (19) of the DSP address line are all valid. The program space of VC5402 is organized into 16 pages, each page is 64k words. The internal 64k-word program space can be accessed directly. When accessing a program area exceeding 64k words, the DSP cannot provide instructions for direct access to the XPC register (the program space is managed by page, and the page address is placed in the XPC register). At this time, the two instructions WRITA and READA can be used to access the high-end program space, either to send data from the data space to the program space, or to send data from the program space to the data space. The accumulator addressing scheme can be used to affect the value of the XPC register.

The advantage of this solution is that there is no need to expand the data area, and the expandable program area of ​​VC5402 can be directly used, which is simple and convenient.

Expansion of data storage space

Offline operation is the most important feature of this system, so the problem of storing offline programs must be considered. In the acquisition and processing system, the FLASH storing the program is mapped to the data space of VC5402. Due to the complexity of the image processing algorithm, the data space of VC5402 alone is difficult to meet the needs, so the data space of VC5402 needs to be expanded.

The FLASH memory SST39VF400A is selected in the system. The capacity of this chip is 256 k × 16 b. It is a low power supply voltage chip with an operating voltage of 3.3 V and a speed of 70 ns. It can realize seamless interface with VC5402 and can store data for more than 100 years. It has the characteristics of large capacity, no data loss after power failure, fast online reading and writing, and whole-chip or page-by-page erasure. At the same time, since the corresponding program has been solidified inside, it only needs to write a specific command word sequence to a specific address when using it, which makes the read and write operations of SST39VF400A very simple and flexible.

In addition, the 64k × 16b SRAM (SRAM3, model CY7C1021) is expanded to store the results of data processing and mapped to the external data space of VC5402. In addition to power and ground, CY7C1021 also has several key signal pins such as CE#, WE#, OE#, BLE, BHE, etc. BLE determines whether the low byte of the chip is valid, that is, whether the low 8 bits of the data bit are valid, while BHE determines whether the high byte (high 8 bits) of the chip is valid. It is valid when the pin is low. Because the data line of VC5402 is 16 bits, that is, the registers and memories used by it should be 16 bits, so the high and low bytes of CY7C1021 should be enabled to make it valid, and BHE and BLE should be grounded through a 360Ω resistor.

The real I/O pins of VC5402 are only 2 BIO# and XF, and they are unidirectional. So its I/O pins are too few to meet the design requirements. This solution expands the data bus D[0:2] of VC5402 into a general I/O port to make up for the lack of I/O ports. The specific method of data space expansion: CPLD is used as an I/O port of DSP, and the data line D[0:2] of DSP is connected to the input end of CPLD. When the I/O selection signals IOSTRB# and IS# of DSP are valid, DSP writes data D[0:2] to CPLD through this I/O, performs logical combination inside CPLD, completes data latching, and when the data selection signal is valid, the latched data is output to generate the paging signal Page[0:2], which is connected to the high-end address of FLASH and SRAM3 respectively.

To access the extended data space, the page signal generated by the CPLD must be used for selection. The 256 k × 16 b FLASH is organized into 8 pages, each page is 32 k words long, and the signals Page2, Page1, and Page0 are responsible for selecting each page of the FLASH. The 64 k × 16 b SRAM3 is divided into 4 pages, each page is 16 k words long, and the signals Page1 and Page0 are responsible for selecting each page. In Flash, the 32 k words of each page are mapped to the 08000 H ~ 0FFFFH area of ​​the data space; in SRAM3, the 16 k words of each page are mapped to the 04000 H ~ 07FFFH area of ​​the data space. The program for generating the page signal is as follows:

CPLD-CS < = DSP-IS OR (NOT DSP -A7) ;

CPLD-CS-IO < = CPLD-CS OR DSP-RW

OR DSP-IOSTRB ;

CPLD-CS-M < = DSP-DS OR DSP-MSTRB

OR DSP-RW;

PROCESS(CPLD-CS-IO ,CPLD-CS-M)

BEGIN

IF CPLD-CS-IO =′0′THEN

QQ < = DSP-D ;

END IF ;

IF CPLD-CS-M =′0′THEN

Q < = QQ ;

END IF ;

END PROCESS ;

After carefully analyzing the allocation characteristics of the data storage space of VC5402 in this solution, the logical combination of VC5402's DSP A15 and data selection signal DS# is used to select FLASH and SRAM3. The specific connection is shown in Figure 3, and its conversion logic is implemented by CPLD programming.

The logic of the read and write control signals of the external FLASH and SRAM is also implemented in the CPLD. The simulation waveform of the control signal required for data storage expansion is shown in Figure 4.

When accessing a certain address in the FLASH space, it should be divided into the following steps:

First, parse the address and perform address segmentation. The lower 15 bits are the page address, and the upper 3 bits are the page selection address.

Secondly, the page selection address is sent to the allocated I/O space PA using the PORTW command. After the strobe signal is enabled, the page address is on the high-end address line of the selected memory.

Finally, use the instruction to access data. Since the data of VC5402 is 16 bits, 16 bits of data are required when calling the data instruction. Here, the lower 15 bits come from the lower 15 bits of the address to be accessed, and the highest bit is filled with zero.

To access the high end of the Flash memory, you must first send data to the CPLD. For example, if you want to address the 70000H storage unit, assuming that the AR3 auxiliary register points to a certain storage unit, the address mapped by the CPLD in the VC5402 I/O space is PA, and the general operation is as follows:

ST # 07H , *AR3

PORTW * AR3 ,PA

In this way, the latch acted by CPLD latches the three-digit number 111. When FLASH is selected, the data 111 is sent to the A15~A17 terminals of FLASH, and then the address 0000H of the DSP memory can be read and written.

DSP expansion I/O port

VC5402 only has these two general I/O pins which are often not enough. DSP provides multiple on-chip devices for some special needs, such as three multi-function serial ports, HPI interface, etc. These on-chip devices are not used in the system, so the DSP extension function can be used to expand the pins of these devices into general I/O ports for system use. For example, the 8-bit parallel data line of the HPI port can be expanded into an 8-bit I/O port for communication with the CPLD. The expansion of these I/O ports is achieved by setting the relevant registers of the DSP accordingly.

In order to realize the interaction between DSP and CPLD, the data line of HPI is used as a general I/O port to realize the expansion of VC5402 I/O port. The specific method of expanding the HPI data line to a general I/O port is: when the HPI interface is not allowed, that is, when the HPIENA pin is at a low level during reset, two memory mapping registers (general I/O control register GPIOCR and general I/O status register GPIOSR) are used to control the input and output of the HPI data pin. The physical addresses of GPIOCR and GPIOSR in DSP are 003CH and 003DH respectively.

To output data 40 H from the extended HPI port, you need to perform the following three steps:

Step 1: During reset, set the HPIENA pin to a low level;

Step 2: Set the value of the general I/O control register GPIOCR to 0x00FF;

Step 3: Set the corresponding bit of the general I/O status register GPIOSR to 01000000, that is, 40H.

The implemented program code is as follows:

STM # 0x003C ,AR3 ; Select control register

ST # 0x00FF , *AR3 ; Set the HPI data terminal to output state

STM # 0x003D ,AR3 ; Select status register

ST # 0x0040 , *AR3 ; Output data 40H

Conclusion

Using CPLD to expand the memory space of VC5402 greatly simplifies the design of hardware circuits and makes programming flexible. When debugging, only the CPLD circuit needs to be debugged, which is simple and convenient. This solution can be extended to the memory expansion of other portable image acquisition and processing systems. 。。