Design and application of a software radio platform based on DSP+FPGA

With the development of wireless communication, various modes of communication systems have emerged. In order to meet the problem of interoperability, the idea of ​​software radio has been proposed. The so-called software radio, its central idea is: to construct an open, standardized, modular universal hardware platform, to complete various communication functions through software, and to make the broadband A/D and D/A converters as close to the antenna as possible, so as to develop a new generation of wireless communication systems with high flexibility and openness. Since software radio can add new functions by adding software modules, and the hardware can also be continuously upgraded with the development of devices, this concept has received widespread attention as soon as it was proposed.

OFDM (orthogonal frequency division multiplexing) is a transmission system with many advantages. It has been widely used. As the research of the fourth generation (4G) wireless communication system enters the substantive stage, OFDM is very likely to become the transmission scheme in 4G. In this context, this paper designs a platform based on software radio and implements the OFDM transmission system on this platform.

System structure design

Currently, due to the limitation of devices, software radio generally adopts the structure of intermediate frequency sampling. This not only takes into account the idea of ​​software radio, but also builds a practical and applicable system at the current device level. The software radio platform in this article also adopts this structure. As the development of wireless communication systems is moving towards high speed and mobility, the design of this platform must also adapt to the requirements of broadband wireless communication systems.

Platform structure

The platform is mainly designed for the intermediate frequency and baseband processing units in the physical layer of the system. The structure of the system is shown in Figure 1. The platform consists of a DSP (TMS320C6414T), two FPGAs (Cyclone EP1C6Q240C8), an up-conversion chip DUC (AD9857), a down-conversion chip DDC (HSP50214B), etc.

Figure 1 Platform structure diagram

According to the characteristics of signal processing modules and data processing of each chip, we assign each communication module to different devices to complete. DSP has a high main frequency and rich internal resources. It supports high-level language programming and is suitable for serial algorithms to complete protocol and baseband processing; FPGA configuration is flexible and changeable. Although the main frequency is not too high, it is used to complete clock distribution, chip settings, interface conversion, etc. in view of its outstanding parallel processing capabilities; AD9857 and HSP50214B are ASICs for up and down conversion. They have a high degree of integration and flexible parameter settings, which can meet the needs of multi-mode digital up and down conversion, data rate conversion and filtering. The following is a brief introduction to the performance of the devices on the platform.

Device Introduction

● DSP

The DSP chip used in the platform is the TMS320C6416T chip from TI. This processor is a 32-bit fixed-point processor with a main frequency of 1GHz and a rich set of peripherals and interfaces. In terms of instruction structure, it has expanded the addressing instructions, bit field instructions, packing and unpacking, control transfer instructions, etc., which enhances the processing power of the chip. When calculating the 2048-point complex FFT operation, it can be completed in about 26,000 clock cycles.

The main modules of 6416T are: 1) two general register groups, 64 32-bit general registers; 2) 8 functional units, 6 ALUs (32/40b), two multipliers (16×16); 3) a total of 8.256Mb of two-level cache internal storage; in addition, there are Viterbi codec coprocessor (VCP) and Turbo codec coprocessor (TCP) not listed in Figure 1. VCP supports 500 channels of 7.95Kb/s AMR, and TCP can handle 6 channels of 2Mb/s 3GPP.

The interfaces include: 1) multi-channel EDMA controller; 2) multi-channel buffered serial port (MCBSP); 3) high-performance external memory interface (EMIF); 4) host port (HPI) that can access the entire memory space of the DSP; they are not listed here one by one.

● Up-conversion chip AD9857

AD9857 is a high-performance digital up-converter with a maximum clock of 200MHz. Depending on the range of the external clock, it can select any intermediate frequency output from 0 to 80MHz. The chip also has a two-level interpolation function, which can achieve 4 times fixed interpolation and 2 to 64 times optional interpolation multiples, facilitating multi-data rate conversion; 14b DAC.

● A/D converter AD9051

The ADC uses ADI's AD9051, with a maximum sampling rate of 60MSPS and 10b output. It can directly sample intermediate frequency signals with lower center frequencies, while bandpass sampling is used for signals with higher intermediate frequencies.

●Down-conversion chip HSP50214B

HSP50214B is the best comprehensive performance among dedicated digital down-conversion chips. In addition to digital down-conversion, it also has a maximum 255-order programmable FIR filter, AGC automatic gain control with a dynamic range of 0 to 96dB, data rate conversion including 4 to 32 times CIC extraction and 5-level HB extraction, as well as FIR1-16 times extraction, coordinate conversion, frequency discrimination and other functions, and has four output forms and flexible interface.

● FPGA

Since the intermediate frequency processing on the platform is completed by ASIC, the FPGA selected is CycloneⅡ EP1C6Q240C8, which is a low-end FPGA chip with only 6000 logic gates. It is mainly used to complete clock distribution, interface conversion, ASIC control word configuration, and as a coprocessor supplement to DSP.

The platform integrates DSP, ASIC and FPGA well, taking into account the versatility and complexity of the system. The application of ASIC reduces the complexity of software design during system configuration.

Implementation of OFDM Transceiver

OFDM technology is one of the current popular technologies. Compared with traditional transmission technologies, OFDM has the following advantages: 1) It reduces the data rate of subcarriers, reduces ISI caused by wireless channels, and effectively reduces multipath interference; 2) It uses several mutually orthogonal subcarriers, and the spectrum overlaps, which maximizes the spectrum efficiency; 3) It uses IFFT and FFT for modulation and demodulation, and the hardware implementation is simple; Therefore, despite the problems of high peak-to-average ratio and sensitivity to frequency deviation, OFDM is still a transmission method with excellent performance. Currently, the standards that use OFDM mainly include digital audio broadcasting (DAB), digital video broadcasting (DVB), European wireless LAN Magic WAND, 802.11, asymmetric digital subscriber line (ADSL), etc. To this end, we have implemented the OFDM transceiver on this platform.

This OFDM system adopts the following baseband and intermediate frequency structure, as shown in Figure 2. In Figure 2, the audio coding adopts the G.729 standard, the scrambling adopts the pseudo-random sequence generated by the 9-bit feedback shift register, and the compression and expansion part is the μ-law compression and expansion transformation, where μ=3. In addition, the number of subcarriers in the system is 2048, the carrier spacing is 1kHz, and the intermediate frequency is 40.96MHz. The structure in the figure includes almost all the processing units that the OFDM system should have, which is representative. On this basis, after necessary parameter modifications, most standard systems can be evolved. In order to facilitate the synchronization processing at the receiving end, a structure similar to DAB is adopted in the frame structure, with 76 symbols per frame, of which the first symbol is a null symbol and the second symbol is a fixed phase reference symbol.

Figure 2 OFDM system block diagram

By analyzing the functions of each module and combining the characteristics of each device on this platform, the implementation of each module is distributed on the platform. Figure 3 shows this distribution method.

Figure 3 OFDM system processing flow

In terms of data interface, the transmitting end DSP sends the framed signal after baseband processing to the FPGA FIFO cache through the EMIF interface, and then the data enters the digital up-converter for 40.96MHz up-conversion. The up-converted data undergoes 4x fixed interpolation and 24x interpolation of CIC and then outputs through D/A to form an OFDM intermediate frequency signal, as shown in Figure 4.

Figure 4 Screenshot of OFDM IF signal spectrum analyzer

The receiving end performs bandpass sampling on the intermediate frequency signal at 32.768MHz, and the digital down-converter performs digital down-conversion on the sampled mirror frequency of 8.192MHz, and then extracts the signal by 16 times to reduce the signal rate to 2M. HSP50214 adopts a parallel direct output mode, and outputs 16b IQ data in two channels respectively. FPGA converts the data into serial and parallel data, and sends the data to DSP through MCBSP for synchronization and baseband processing to obtain the original transmission information.

in conclusion

This paper proposes a software radio platform based on DSP, FPGA and ASIC, and completes the baseband and intermediate frequency design of the OFDM system on this experimental platform. After actual verification, the system runs well and effectively supports multiple communication modes. It is a widely used software radio platform. Currently, the baseband pre-distortion technology of the power amplifier is being studied to further improve the system performance.