Hardware Design of Vehicle Assisted Driving System Based on ADSP-BF561

introduction

Since the 1980s, electronic technology and computer technology have developed rapidly, and the research on automobile driving safety has also entered a new field. Its development direction is mainly reflected in the research on active and passive safety of intelligent automobiles, among which safe assisted driving is one of the important contents of the current international intelligent transportation system research. At present, the application of CCD or CMOS cameras in the field of vehicle safety assisted driving with excellent performance and low-cost DSP processors is also increasing. Among them, ADI's Blackfin series processors are based on the Micro Signal Architecture (MSA) jointly developed by ADI and Intel. They are used in traffic sign recognition, intelligent lighting control, lane change assistance, blind spot recognition, rearview cameras and parking assistance, adaptive cruise control (Adaptive Cruise Control, ACCl, night assisted driving and intelligent airbags, etc. Therefore, the hardware development of the Black6n series processors provides a good research platform and development environment for the entire system.

1. Vehicle Assisted Driving System Framework Design

Figure 1 System overall framework

The main purpose of vehicle assisted driving is to improve the safety of automobile driving. Various sensors installed on the vehicle are used to obtain information such as vehicle, road conditions, and surrounding vehicle conditions. Effective warning signals are provided to the driver. And under certain conditions, the vehicle is safely controlled. The system is mainly composed of a visual system, a radar system, an assisted driving control system, a mechanical automatic transmission control system, an engine control system, and a braking control system. The sensors that perceive the vehicle status include brake pedal displacement sensor, accelerator pedal displacement sensor, steering angle sensor, wheel speed sensor, and acceleration sensor. Its frame structure is shown in Figure 1.

1.1 Environmental Perception System

The visual sensor uses an AIR-7010C CCD camera. It is connected to the ADSP-BF561 parallel input and output peripheral interface unit through ADV7183 for video decoding. The radar system uses the LD-ML multi-layer laser radar system of IBEO. The image data after the visual processing algorithm is fused with the radar data. Finally, the effective information of the obstacle is obtained and sent to the auxiliary driving control unit through the CAN bus for strategic control.

1.2 Low-level control system

The system obtains effective vehicle driving status information and vehicle driving environment information through the CAN bus, monitors the longitudinal and lateral driving safety of the vehicle, and intervenes in the longitudinal driving of the vehicle under certain driving conditions. The auxiliary driving control strategy unit controls the engine speed, the gear position and clutch of the mechanical automatic transmission (fAM, I'), and the braking system by obtaining environmental perception sensors and vehicle status sensors.

2 Hardware System Composition and Design

The Blackfin processor architecture is based on a 10-level RISC MCU/DSP pipeline and a hybrid 16/32-bit instruction set architecture designed for optimal code density. In addition, it also contains instructions for accelerating video and image processing. Therefore, the Blackfin series of processors are used in communications, images, voice, etc. ADSP-BF561 is currently the highest-performance processor in the Blackfin family, and its features are as follows:

1) Two symmetrical high-performance Blackfin cores with a maximum frequency of up to 600MHz;

2) Each core includes two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, and a 40-bit shifter:

3) Core voltage 0.8V-1.2V, compatible with 3.3V and 2.5VI/O;

4) 328K Bytes on-chip memory. Each core has 32Kbytes of L1 instruction SRAM/Cache, 64Kbytes of L1 data SRAM/Cache, 4KBytes of L1 temporary data SRAM, and 128Kbytes of shared L2 SRAM:

5) 2 parallel input/output peripheral interface units (PPI), supporting ITU-R656 video data format; 2 dual-channel full-duplex synchronous serial interfaces, supporting 8 stereo channels; 2 16-channel DMA controllers and 1 internal memory DMA controller; 12 general-purpose 32-bit timers; UART supporting IrDA; 2 "watchdog" timers; 48 programmable flag pins; on-chip PLL with 1x-63x frequency multiplication.

2.1 Power supply and reset circuit

When designing the power supply circuit, we need to consider the load capacity, reliability and stability of the power supply. At the same time, we need to consider how many types of power supplies the system needs. The external I/O power supply voltage of ADSP-BF56l is 3.3V. The core power supply voltage is 1.2V. Therefore, the system needs +5V, +3.3V, and +1.2V. First, the +24v on the car is converted to +5V through DC-DC2405. Then, the +5V is converted to +3.3V through LT1765. ADP3336 converts +3.3v to +1.2v. The reset circuit uses the ADM708 reset chip. A manual button is added to the circuit to realize the manual reset function and facilitate program debugging.

2.2 Clock circuit

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Active crystal oscillator has good signal quality, is relatively stable, is easy to connect and does not require complex configuration circuits. Therefore, the ADSP-BF561 system input clock uses a 30MHz external active crystal oscillator and then uses its internal phase-locked loop PLL to multiply the frequency accordingly as the bus frequency of ADSP-BF561 and the clock frequency of SDRAM. At the same time, due to the parallel input, output peripheral interface 13 and video codec chip clock requirements, the 27MHz active crystal oscillator needs to be divided into 4 outputs through IDT2305.

2.3 Storage expansion circuit

SDRAM is a synchronous addressable memory, consisting of blocks, rows and columns. All read operations are locked to a processor source clock. Once the processor initializes the SDRAM, the memory must be constantly updated to ensure that its state is maintained. The clock rate of SDRAM is variable. The most commonly used in industry are PCI00 and PCI33, with the highest clock frequencies of 100MHz and 133MHz respectively. ADSP-BF561 has a seamless connection between the SDRAM controller (SDC) and SDRAM. The connection is shown in Figure 2(a). The system uses MT48LCl6M16A2, with a capacity of 32MHz and a maximum frequency of 133MHz.

ADSP-BF561 has an asynchronous memory controller (AMc) that shares data and address pins with the SDRAM controller. After power-on reset or software initialization reset, the processor samples the reset configuration register BMODE pin to perform the boot function. The system uses BMODEIO as the 8116-bit Flash boot mode, and selects NORFLASH as the boot code memory. The selected chip is the M29W640DT with a capacity of 8MB. Its connection method is shown in Figure 2(b).

a) SDRAM

b) Flash

Figure 2 Memory connection

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2.4 Parallel input/output peripheral interface circuit

ADSP-BF561 provides two parallel interfaces (PPI) that can be directly connected to parallel A/D and D/A converters, video encoders and decoders that comply with the ITU-601/656 standard, and other general peripherals. Each PPI includes a dedicated clock pin generated by the clock circuit. 3 frame synchronization pins and 16 data pins. The video decoder ADV7183 is connected to the PPl0 of ADSP-BF561. The video encoder ADV7179 is connected to the PPll of ADSP-BF561. This realizes the environmental perception sensing and human-machine interface functions in the vehicle assisted driving system. The connection is shown in Figure 3.

Figure 3 Parallel input/output connections

2.5 CAN interface circuit

CAN (Controller Area Network) bus, namely controller area network bus, is a serial communication network that effectively supports distributed control or real-time control. It has been widely used in control fields such as automobiles. It uses the seamless connection between the ADSP-BF561 processor serial SPI bus interface unit and the CAN controller MCP2515 chip. By operating the internal registers of the conversion chip, the data is sent and received through the CAN receiver SN65230 chip.

3 Software and Experimental Analysis

The hardware design of the system is the basis for subsequent code writing and algorithm implementation. Therefore, after completing the hardware development of the above system, the underlying driver module and system software framework are written, and the visual processing algorithm is transplanted. ADI provides a complete set of software development tools Visual DSP++. Using the Visual DSP++ project management environment, programmers can easily develop and debug applications. At the same time, the compiler of the development software can effectively convert C and C++ codes into Blackfin DSP assembly code. The acquisition results are shown in Figure 4(a).

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ADSP-BF561 is a symmetric dual-core processor, so different cores are used to handle different tasks when programming, and debugging software is written according to the hardware interface. CoreA mainly includes setting the clock frequency, initializing the SDRAM controller, initializing the video codec, initializing PPI0 and interrupts, and enabling PPIO. It is acquired in ITU656 mode, and the acquired frames are stored in SDRAM: CoreB mainly includes setting the clock frequency, initializing PPI1 and interrupts, enabling PPI1, and executing video output in general output mode. The software flow is shown in Figure 4(b).

a) Collection interface

b) Software Process

Figure 4 Collection interface and flow chart

4 Conclusion

This system uses ADI's powerful media processor ADSP-BF561. After completing the minimum system and extended function hardware development, code and algorithm development can be easily carried out on this hardware platform. The visual processing system plays an important role in the entire system design. The successful completion of its hardware design can shorten the development cycle, reduce development costs and lay a solid foundation for the development of vehicle assisted driving systems.

The author's innovation: Using the digital signal processor ADSP-BF561 to design the hardware of the vehicle assisted driving system, realizing real-time video acquisition and display, and providing an experimental platform for the development of vehicle assisted driving vision processing algorithms.

Economic benefits: This system has been tested on a Dongfeng heavy-duty vehicle and has good application prospects.